Multi-cavity package having single metal flange
A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.
1. A multi-cavity package, comprising:
a single metal flange having first and second opposing main surfaces;
a circuit board attached to the first main surface of the single metal flange, the circuit board comprising:
a first surface facing the single metal flange, and a second surface facing away from the first surface;
a plurality of openings exposing respective regions of the first main surface of the single metal flange;
a lateral extension that overhangs the single metal flange;
a metal trace disposed on the second surface of the circuit board, extending onto the lateral extension, and configured to provide an input or output electrical pathway to a semiconductor die when the semiconductor die is disposed in one of the openings and is attached to the main surface of the single metal flange.
2. The multi-cavity package of claim 1 wherein the metal trace further extends onto an edge face of the lateral extension.
3. The multi-cavity package of claim 2 , wherein the metal trace further extends from the edge face onto a bottom face of the lateral extension adjacent to the single metal flange.
4. The multi-cavity package of claim 1 , further comprising the semiconductor die and a further semiconductor die disposed in respective ones of the openings and attached to the first main surface of the single metal flange.
5. The multi-cavity package of claim 4 , wherein:
the semiconductor die is an amplifier die; or
the further semiconductor die is the amplifier die; or
each of the semiconductor die and the further semiconductor die is a respective amplifier die.
6. The multi-cavity package of claim 4 , wherein the circuit board further comprises a further metal trace configured to electrically interconnect the semiconductor dies to form a circuit.
7. The multi-cavity package of claim 6 , wherein the metal trace and further metal trace are comprised in a single layer disposed on the second surface of the circuit board.
8. The multi-cavity package of claim 4 , wherein at least one of the semiconductor dies is a transistor die having a first terminal attached to the single metal flange through the opening in the circuit board in which that semiconductor die is disposed, and a second terminal and a third terminal at a side of the transistor die opposite the first terminal.
9. The multi-cavity package of claim 8 , wherein the second terminal of the transistor die is electrically connected to a first one of the metal traces and the third terminal of the transistor die is electrically connected to a second one of the metal traces.
10. The multi-cavity package of claim 4 , wherein at least one of the semiconductor dies is a passive semiconductor die devoid of active devices.
11. The multi-cavity package of claim 4 , wherein:
a first one of the semiconductor dies is a driver stage die of a Doherty amplifier circuit;
a second one of the semiconductor dies is a main amplifier die of the Doherty amplifier circuit;
the multi-cavity package further comprises a peaking amplifier die of the Doherty amplifier circuit, the peaking amplifier die disposed in a corresponding one of the openings in the circuit board and attached to the first main surface of the single metal flange;
an output of the driver stage die and an input of the main amplifier die and an input of the peaking amplifier die are electrically interconnected via an inter-stage match; and
an output of the main amplifier die and an output of the peaking amplifier die are electrically connected to a Doherty combiner.
12. The multi-cavity package of claim 11 , further comprising a phase shifter or an attenuator at the input of the driver stage die.
13. The multi-cavity package of claim 4 , wherein:
a first one of the semiconductor dies is a driver stage die of a power amplifier circuit;
a second one of the semiconductor dies is a power stage die of the power amplifier circuit;
the multi-cavity package further comprises an inter-stage match between an output of the driver stage die and an input of the power stage die; and
a second one of the metal traces is electrically connected to an output of the power stage die.
14. The multi-cavity package of claim 13 , wherein the power amplifier circuit is an RF power amplifier circuit and the multi-cavity package further comprises an antenna of the RF power amplifier circuit electrically connected to an output of the power stage die.
15. The multi-cavity package of claim 4 , further comprising one or more additional semiconductor dies attached to a surface of the circuit board facing away from the single metal flange and electrically connected to one or more of the semiconductor dies disposed in the openings of the circuit board.
16. The multi-cavity package of claim 1 , wherein the lateral extension forms an interface for attaching the multi-cavity package to another structure.
17. The multi-cavity package of claim 1 , further comprising at least one via that extends through the lateral extension.
18. The multi-cavity package of claim 1 , wherein the circuit board further comprises:
a further lateral extension overhanging the single metal flange and away from the lateral extension;
a circuit comprising an electrical input pathway extending onto the lateral extension, and an electrical output pathway extending onto the further lateral extension.
19. A method of manufacturing a multi-cavity package, the method comprising:
providing a single metal flange having first and second opposing main surfaces;
attaching a circuit board to the first main surface of the single metal flange, such that:
a first surface of the circuit board faces the single metal flange;
a second surface of the circuit board faces away from the single metal flange;
a plurality of openings in the circuit board expose different regions of the first main surface of the single metal flange;
a lateral extension of the circuit board overhangs the single metal flange; and
a metal trace disposed on the second surface of the circuit board and extending onto the lateral extension is arranged to provide an input or output electrical pathway to a semiconductor die when the semiconductor die is disposed in one of the openings and is attached to the main surface of the single metal flange.