Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.
1. A high-electron mobility transistor comprising:
a substrate layer;
a first buffer layer provided on the substrate layer;
a barrier layer provided on the first buffer layer;
a source including a first portion provided on the barrier layer;
a drain provided on the barrier layer;
a gate provided on the barrier layer;
a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer, and the p-type material layer is arranged at the surface of the substrate layer adjacent a surface of the first buffer layer;
an etched recess in at least the first buffer layer and the barrier layer; and
the source comprises a second portion having a p-type material contact arranged in the etched recess and the second portion having the p-type material contact arranged on and electrically coupled to the p-type material layer that is arranged at the surface of the substrate layer adjacent the surface of the first buffer layer and in the substrate layer,
wherein the p-type material layer is provided in the substrate layer;
wherein a two-dimensional electron gas (2DEG) is induced at a heterointerface between the first buffer layer and the barrier layer when the gate is appropriately biased; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located along a vertical axis of the drain perpendicular to the surface of the substrate layer.
2. The transistor of claim 1 , further comprising:
a protective layer, wherein the gate is arranged in part on the barrier layer and the gate is arranged in part on the protective layer;
wherein the p-type material layer is structured and arranged to minimize drain lag effects; and
wherein the p-type material layer comprises aluminum implanted in the substrate layer.
3. The transistor of claim 1 ,
wherein the p-type material layer comprises aluminum implanted in the substrate layer; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate and the p-type material layer is not located along a vertical axis of the drain perpendicular to the surface of the substrate layer.
4. The transistor of claim 1 , further comprising:
a nucleation layer arranged on the substrate layer and the first buffer layer is arranged on the nucleation layer,
wherein the substrate layer comprises Gallium Nitride; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends 0% to 50% of a distance between the gate and the drain.
5. The transistor of claim 1 , wherein:
the substrate layer comprises Silicon Carbide;
the first buffer layer comprises Gallium Nitride;
the barrier layer comprises Aluminum Gallium Nitride; and
the p-type material layer is provided adjacent a surface of the first buffer layer; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate and the p-type material layer is not located along a vertical axis of the drain perpendicular to the surface of the substrate layer.
6. A high-electron mobility transistor comprising:
a substrate layer;
a first buffer layer provided on the substrate layer;
a barrier layer provided on the first buffer layer;
a source including a first portion provided on the barrier layer;
a drain provided on the barrier layer;
a gate provided on the barrier layer;
a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer, and the p-type material layer is arranged at the surface of the substrate layer adjacent a surface of the first buffer layer;
an etched recess in at least the first buffer layer and the barrier layer;
the source comprises a second portion having a p-type material contact arranged in the etched recess and the second portion having the p-type material contact arranged on and electrically coupled to the p-type material layer that is arranged at the surface of the substrate layer adjacent the surface of the first buffer layer and in the substrate layer;
a second buffer layer provided on the first buffer layer;
a protective layer provided on the barrier layer; and
a nucleation layer arranged on the substrate layer and the first buffer layer is arranged on the nucleation layer,
wherein the p-type material layer is provided in the substrate layer;
wherein a two-dimensional electron gas (2DEG) is induced at a heterointerface between the first buffer layer and the barrier layer when the gate is appropriately biased;
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located along a vertical axis of the drain perpendicular to the surface of the substrate layer; and
wherein the p-type material layer is further arranged in the substrate layer with the first buffer layer arranged on the p-type material layer and the substrate layer.
7. The transistor of claim 1 , further comprising:
a field plate structure extending a distance away from an edge of the gate,
wherein the p-type material layer length parallel to the surface of the substrate layer extends 0% to 50% of a distance between the gate and the drain;
the substrate layer comprises Silicon Carbide;
the first buffer layer comprises Gallium Nitride;
the barrier layer comprises Aluminum Gallium Nitride; and
the p-type material layer is provided adjacent a surface of the first buffer layer.
8. A process of making high-electron mobility transistor comprising:
providing a substrate layer;
providing a first buffer layer on the substrate layer;
providing a barrier layer arranged on the first buffer layer; and
providing a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer such that the p-type material layer is not located along a vertical axis of a drain perpendicular to the surface of the substrate layer, and the p-type material layer is arranged at the surface of the substrate layer adjacent a surface of the first buffer layer;
etching a recess in at least the first buffer layer and the barrier layer; and
forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer that is arranged at the surface of the substrate layer adjacent the surface of the first buffer layer and in the substrate layer,
wherein the p-type material layer is provided in the substrate layer; and
wherein a two-dimensional electron gas (2DEG) is induced at a heterointerface between the first buffer layer and the barrier layer when a gate is appropriately biased.
9. The process of claim 8 , further comprising neutralizing a portion of the p-type material layer in the substrate layer such that the p-type material layer is not located along a vertical axis of a drain perpendicular to the surface of the substrate layer.
10. The process of claim 8 , further comprising:
forming a protective layer; and
arranging the gate in part on the barrier layer and in part on the protective layer;
wherein providing the p-type material layer comprises one of the following:
implanting and annealing aluminum to form the p-type material layer in the substrate layer; or
doping the substrate layer with aluminum to form the p-type material layer,
wherein the p-type material layer is formed adjacent a surface of the first buffer layer.
11. The process of claim 8 , further comprising:
etching the p-type material layer to the length less than the length of the substrate layer such that the p-type material layer is not located along a vertical axis of a drain perpendicular to the surface of the substrate layer,
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate toward the drain such that the p-type material layer is not located along a vertical axis below the drain perpendicular to the surface of the substrate layer.
12. The process of claim 8 , wherein providing the p-type material layer comprises one of the following:
implanting and annealing aluminum to form the p-type material layer in the substrate layer; or
doping the substrate layer with aluminum to form the p-type material layer,
wherein the p-type material layer is formed adjacent a surface of the first buffer layer; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends 0% to 50% of a distance between the gate and the drain.
13. The process of claim 8 , further comprising etching the p-type material layer to the length less than the length of the substrate layer such that the p-type material layer is not located along a vertical axis of a drain perpendicular to the surface of the substrate layer.
14. The process of claim 8 , further comprising:
providing a second buffer layer formed on the first buffer layer;
providing a protective layer formed on the barrier layer; and
providing a nucleation layer arranged on the substrate layer,
wherein the providing the p-type material layer further comprises: providing the p-type material layer in the substrate layer with the first buffer layer arranged on the p-type material layer and the substrate layer.
15. The transistor of claim 1 , further comprising:
forming a nucleation layer on the substrate layer and arranging the first buffer layer on the nucleation layer,
wherein:
the substrate layer comprises Silicon Carbide; and
the p-type material layer comprises Aluminum p-dopants implanted in the substrate layer.
16. The transistor of claim 1 , wherein:
the first buffer layer comprises Gallium Nitride; and
the barrier layer comprises Aluminum.
17. The transistor of claim 1 , further comprising a field plate structure extending a distance away from an edge of the gate.
18. The process of claim 8 , further comprising:
implanting aluminum p-dopants for the p-type material layer in the substrate layer,
wherein the substrate layer comprises Silicon Carbide; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate toward the drain such that the p-type material layer is not located along a vertical axis below the drain perpendicular to the surface of the substrate layer.
19. The process of claim 8 , wherein:
the first buffer layer comprises Gallium Nitride; and
the barrier layer comprises Aluminum; and
the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate toward the drain such that the p-type material layer is not located along a vertical axis below the drain perpendicular to the surface of the substrate layer.
20. The process of claim 8 , further comprising:
forming a protective layer;
arranging a gate in part on the barrier layer and in part on the protective layer; and
forming a field plate structure extending a distance away from an edge of the gate.
21. The transistor of claim 1 , further comprising:
a field plate structure extending a distance away from an edge of the gate,
wherein the p-type material layer length parallel to the surface of the substrate layer extends at least from the source past the gate toward the drain such that the p-type material layer is not located along a vertical axis below the drain perpendicular to the surface of the substrate layer.
22. The process of claim 8 , further comprising:
implanting the p-type material layer with aluminum in the substrate layer such that the p-type material layer is formed adjacent a surface of the first buffer layer;
forming a protective layer;
arranging a gate in part on the barrier layer and in part on the protective layer; and
forming a field plate structure extending a distance away from an edge of the gate,
wherein the p-type material layer is structured and arranged to minimize drain lag effects; and
wherein the p-type material layer length parallel to the surface of the substrate layer extends 0% to 50% of a distance between the gate and the drain.
23. The process of claim 22 , further comprising:
implanting aluminum to form the p-type material layer in the substrate layer such that the p-type material layer is formed adjacent a surface of the first buffer layer,
wherein the p-type material layer is structured and arranged to minimize drain lag effects.