High electron mobility transistors having improved contact spacing and/or improved contact vias
A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.
1. A high electron mobility transistor (HEMT), comprising:
a substrate;
a semiconductor structure on the substrate;
a first via and a second via, each extending in the substrate and the semiconductor structure;
a first ohmic source contact on the first via and a second ohmic source contact on the second via;
a drain contact on the semiconductor structure and between, in plan view, the first via and the second via; and
a gate contact between the first ohmic source contact and the drain contact, wherein a width of the first via decreases as the first via extends from a bottom surface of the substrate to a top surface of the substrate.
2. The HEMT of claim 1 , further comprising a backmetal layer within the first via,
wherein the backmetal layer directly contacts a bottom surface of the first ohmic source contact, and
wherein a contact area between the backmetal layer and the bottom surface of the first ohmic source contact is fifty percent or more of an area of the bottom surface of the first ohmic source contact.
3. The HEMT of claim 1 , wherein an area of a largest cross-section of the first via in a direction parallel to a top surface of the substrate is less than 1000 μm 2 .
4. The HEMT of claim 1 , wherein the first ohmic source contact is in a recess in an upper surface of the semiconductor structure.
5. The HEMT of claim 1 , wherein a thickness of the substrate is 75 μm or less.
6. The HEMT of claim 1 , wherein the semiconductor structure comprises a channel layer and a barrier layer on the channel layer.
7. The HEMT of claim 6 , wherein the first via extends through the channel layer and the barrier layer.
8. A high electron mobility transistor (HEMT), comprising:
a substrate comprising a first surface and a second surface on opposing sides of the substrate;
a channel layer on the first surface of the substrate;
a barrier layer on the channel layer;
a source contact comprising a first ohmic contact on an upper surface of the barrier layer;
a plurality of drain contacts and a plurality of gate contacts on the barrier layer; and
a via extending from the second surface of the substrate to the first ohmic contact, wherein the via is between, in plan view, one of the drain contacts and one of the gate contacts.
9. The HEMT of claim 8 , further comprising a backmetal layer within the via,
wherein the backmetal layer directly contacts a bottom surface of the first ohmic contact, and
wherein a contact area between the backmetal layer and the bottom surface of the first ohmic contact is fifty percent or more of an area of the bottom surface.
10. The HEMT of claim 8 , wherein an area of a largest cross-section of the via in a direction parallel to the first surface of the substrate is less than 1000 μm 2 .
11. The HEMT of claim 8 , wherein the one of the drain contacts and the one of the gate contacts each extend in a first direction, and
wherein the via is below a portion of the source contact that is between the one of the drain contacts and the one of the gate contacts in a second direction that is perpendicular to the first direction.
12. The HEMT of claim 8 , wherein the first ohmic contact is in a recess in the upper surface of the barrier layer.
13. The HEMT of claim 8 , wherein the via extends through the channel layer and the barrier layer.
14. The HEMT of claim 8 , wherein a thickness of the substrate is 75 μm or less.
15. A high electron mobility transistor (HEMT), comprising:
a substrate;
a semiconductor structure on the substrate;
a first ohmic source contact and a second ohmic source contact on the semiconductor structure;
a drain contact on the semiconductor structure between the first ohmic source contact and the second ohmic source contact; and
a via extending between a bottom surface of the substrate and the first ohmic source contact,
wherein a distance between the first ohmic source contact and the second ohmic source contact is 60 μm or less, and
wherein the via is located below a first portion of the first ohmic source contact, and
wherein a second portion of the drain contact is between the first portion of the first ohmic source contact and the second ohmic source contact.
16. The HEMT of claim 15 , wherein the semiconductor structure comprises a channel layer and a barrier layer on the channel layer, and
wherein the HEMT further comprises a doped well in the barrier layer adjacent the first ohmic source contact.
17. The HEMT of claim 15 , wherein an area of a largest cross-section of the via in a direction parallel to the bottom surface of the substrate is less than 1000 μm 2 .
18. The HEMT of claim 15 , further comprising a backmetal layer within the via that contacts the first ohmic source contact.
19. The HEMT of claim 18 ,
wherein a contact area between the backmetal layer and a bottom surface of the first ohmic source contact is fifty percent or more of an area of the bottom surface.