IP Library Patent Application 18826969
Patent Application
App. No. 18/826,969

SEMICONDUCTOR DEVICES WITH DRAIN-SOURCE CONNECTION FOR AVALANCHE BREAKDOWN

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Quick Facts
Patent No.
US None
App. No.
18/826,969
Abstract

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

Claims (43)

1 . A vertical junction field effect (JFET) semiconductor device, comprising:

a drift layer;

a channel layer on the drift layer;

a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches comprises gate contact regions;

a source metallization on the mesas; and

a second trench different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

2 . The vertical JFET semiconductor device of claim 1 , wherein the source metallization extends into the second trench.

3 . The vertical JFET semiconductor device of claim 1 , further comprising:

an electrical contact in the second trench, wherein the electrical contact is electrically connected to the source metallization outside the second trench.

4 . The vertical JFET semiconductor device of claim 1 , wherein the second trench extends deeper into the drift layer than the first plurality of trenches.

5 . The vertical JFET semiconductor device of claim 1 , wherein the second trench extends about two to three times deeper into the drift layer than the first plurality of trenches.

6 . The vertical JFET semiconductor device of claim 1 , wherein corners of a pair of mesas of the plurality of mesas adjacent the second trench are rounded, angled or chamfered.

7 . The vertical JFET semiconductor device of claim 1 , wherein a first one of the first plurality of trenches is directly adjacent a second one of the first plurality of trenches, wherein a distance between the first and second ones of the first plurality of trenches is greater than a distance between the second trench and a third one of the first plurality of trenches that is directly adjacent to the second trench.

8 . The vertical JFET semiconductor device of claim 1 , further comprising a doped region beneath the second trench, wherein the doped region has a conductivity type that is the same as a conductivity type of a drift region of the vertical JFET semiconductor device.

9 . The vertical JFET semiconductor device of claim 8 , wherein the second trench is deeper than the first plurality of trenches.

10 . The vertical JFET semiconductor device of claim 8 , wherein the doped region has a greater doping concentration than the drift region.

11 . The vertical JFET semiconductor device of claim 8 , wherein the doped region has a doping concentration greater than about 1.25 times a doping concentration of the drift region.

12 . The vertical JFET semiconductor device of claim 1 , wherein the second trench is enclosed by a single mesa.

13 . The vertical JFET semiconductor device of claim 1 , further comprising a plurality of second trenches, wherein the source metallization is electrically connected to the drift layer at bottoms of the plurality of second trenches.

14 . The vertical JFET semiconductor device of claim 13 , wherein bottoms of the plurality of second trenches are conductively connected to the source metallization.

15 . The vertical JFET semiconductor device of claim 14 , wherein a number of the first plurality of trenches is about equal to a number of the plurality of second trenches.

16 . The vertical JFET semiconductor device of claim 14 , wherein each of the plurality of second trenches is adjacent one of the first plurality of trenches.

17 . A vertical junction field effect (JFET) semiconductor device, comprising:

a drift layer;

a channel layer on the drift layer;

a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches comprise gate contact regions; and

a source metallization on the plurality of alternating trenches and mesas;

wherein the source metallization is electrically connected to the drift layer at a bottom of a second trench that is different from the first plurality of trenches.

18 . The vertical JFET semiconductor device of claim 17 , further comprising a plurality of second trenches, wherein the source metallization is electrically connected to the drift layer at bottoms of the plurality of second trenches.

19 . A vertical junction field effect (JFET) semiconductor device, comprising:

a drift layer;

a channel layer on the drift layer; and

a plurality of alternating trenches and mesas in the channel layer within an active region of the device, wherein the plurality of trenches comprise a first plurality of the trenches having a first depth and a second plurality of trenches in having a second depth that is greater than the first depth.

20 . The vertical JFET semiconductor device of claim 19 , further comprising:

gate contact regions within the first plurality of trenches; and

a source metallization, wherein the source metallization is electrically connected to the drift layer at bottoms of the second plurality of trenches.

21 . A method of forming vertical junction field effect (JFET) semiconductor device, comprising:

providing a drift layer;

forming a channel layer on the drift layer; and

forming a plurality of alternating trenches and mesas in the channel layer within an active region of the device, wherein the plurality of trenches comprise a first plurality of the trenches having a first depth and a second plurality of trenches having a second depth that is greater than the first depth.

22 . The method of claim 21 , further comprising:

forming gate contacts within the first plurality of trenches; and

forming a source metallization on the device, wherein the source metallization is electrically connected to the drift layer at bottoms of the second plurality of trenches.

Assignments (8)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 69180/0437 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0088 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Oct 17, 2024
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 069180/0437 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2024
From: POTERA, RAHUL R.; RYU, SEI-HYUNG
To: WOLFSPEED, INC.
Reel/Frame 068513/0259 →