Granted Patent B2

US 7,391,057 · App. 11/131,509 · Granted Jun 24, 2008

Abstract

Claims (48)

1. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type;

a first region of SiC on the first SiC layer and having the second conductivity type;

a second region of SiC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;

a second SiC layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC substrate; and

first and second contacts on the first region of SiC and the second SiC layer, respectively.

2. The device of claim 1 , wherein the voltage blocking substrate comprises a 4H—SiC high purity substrate having a carrier concentration no greater than about 1.0×10 15 cm −3 .

3. The device of claim 2 , wherein the voltage blocking substrate has a thickness of greater than about 100 μm.

4. The device of claim 1 , wherein the first conductivity type comprises p-type SiC and the second conductivity type comprises n-type SiC.

5. The device of claim 1 , wherein the first conductivity type comprises n-type SiC and the second conductivity type comprises p-type SiC.

6. The device of claim 1 :

wherein the first SiC layer has a carrier concentration of from about 1.0×10 15 cm −3 to about 1.0×10 19 cm −3 ; and

wherein the second SiC layer has a carrier concentration of from about 1.0×10 17 cm −3 to about 1.0×10 21 cm −3 ; and

wherein the first region of SiC has a carrier concentration of from about 1.0×10 16 cm −3 to about 1.0×10 21 cm − .

7. The device of claim 1 :

wherein the first SiC layer has a thickness of from about 0.1 μm to about 20.0 μm;

wherein the second SiC layer has thickness of from about 0.5 μm to about 50.0 μm; and

wherein the first region of SiC has a thickness of from about 0.1 μm to about 10.0 μm.

8. The device of claim 1 , wherein the SiC device comprises a thyristor, wherein the first region of SiC comprises an anode region of the thyristor, wherein the second region of SiC comprises a gate region of the thyristor and wherein the second SiC layer comprises a cathode region of the thyristor.

9. The device of claim 8 , further comprising a third contact on the second region of SiC, wherein the first, second and third contacts comprise an anode contact, a cathode contact and a gate contact, respectively, the device further comprising first, second and third overlayers on the first, second and third contacts, respectively.

10. The device of claim 1 , wherein the second region of SiC has a carrier concentration of from about 1.0×10 17 cm −3 to about 1.0×10 21 cm −3 and extends into the first SiC layer from about 0.1 μm to about 2.0 μm.

11. The device of claim 1 , wherein the voltage blocking substrate is a bi-directional voltage blocking layer and has an edge termination structure.

12. The device of claim 11 , wherein the voltage blocking substrate is a boule grown substrate.

13. The device of claim 1 , wherein the edge termination provides:

a first blocking junction between the first surface of the voltage blocking substrate and the first SiC layer; and

a second blocking junction between the second surface of the voltage blocking substrate and the second SiC layer.

14. A silicon carbide (SiC) thyristor, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SIC substrate having a second conductivity type;

a SiC anode region on the first SiC layer and having the second conductivity type;

a SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the SiC anode region;

a SiC cathode layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC substrate; and

an anode contact, a gate contact and a cathode contact on the SiC anode region, the SiC gate region and the SiC cathode layer, respectively.

15. The thyristor of claim 14 , wherein the voltage blocking substrate is a bi-directional voltage blocking layer and has a edge termination structure.

16. The thyristor of claim 15 , wherein the edge termination structure provides:

a first blocking junction between the first surface of the voltage blocking substrate and the first SiC layer; and

a second blocking junction between the second surface of the voltage blocking substrate and the SiC cathode layer.

17. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;

a first region of SiC on the first SiC layer and having the second conductivity type;

a second region of SIC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;

a second SiC layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC epilayer; and

first and second contacts on the first region of SiC and the second SiC layer, respectively.

18. A silicon carbide (SiC) thyristor, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;

a SiC anode region on the first SiC layer and having the second conductivity type;

a SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the SiC anode region;

a SiC cathode layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC epilayer; and

an anode contact, a gate contact and a cathode contact on the SiC anode region, the SiC gate region and the SiC cathode layer, respectively.

Assignments (8)