Electronic device structure with a semiconductor ledge layer for surface passivation
View Patent ↗Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
1. An electronic device comprising:
a structure comprising a plurality of semiconductor layers having alternating doping types, the plurality of semiconductor layers comprising:
a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device; and
one or more contact layers on the base layer that form a second contact region of the electronic device and that are of a second doping type that is opposite the first doping type; and
a semiconductor ledge layer directly on the base layer that passivates interface charge at the surface of the base layer, wherein the semiconductor ledge layer is of the first doping type.
2. The electronic device of claim 1 wherein the semiconductor ledge layer is lightly doped.
3. The electronic device of claim 2 wherein a doping level of the semiconductor ledge layer is in a range of about and including 5×10 15 to 1×10 17 carriers per centimeter cubed (cm 3 ).
4. The electronic device of claim 2 wherein the semiconductor ledge layer is on the base layer between the first contact region and the second contact region and one or more sidewall surfaces of the one or more contact layers adjacent to the surface of the base layer.
5. The electronic device of claim 2 wherein the semiconductor ledge layer is on the base layer between the first contact region and the second contact region.
6. The electronic device of claim 2 wherein a doping level and a thickness of the semiconductor ledge layer are optimized to compensate for the interface charge at the surface of the base layer.
7. The electronic device of claim 6 wherein the doping level of the semiconductor ledge layer is in a range of about and including 5×10 15 to 1×10 17 carriers per centimeter cubed (cm 3 ) and the thickness of the semiconductor ledge layer is in a range of about and including 1000 to 3000 Angstroms.
8. The electronic device of claim 1 wherein the semiconductor ledge layer is a highly doped semiconductor ledge layer on the surface of the base layer.
9. The electronic device of claim 8 wherein the highly doped semiconductor ledge layer has a doping level that is greater than or equal to about 1×10 18 carriers per centimeter cubed (cm 3 ).
10. The electronic device of claim 9 wherein the base layer has a doping level in a range of about and including 1×10 17 to 1×10 18 carriers per cm 3 .
11. The electronic device of claim 8 wherein a doping level of the highly doped semiconductor ledge layer is greater than a doping level of the base layer such that a doping gradient from the highly doped semiconductor ledge layer to the base layer creates an electric field that repels charge carriers injected into the base layer away from the interface charge at the surface of the base layer.
12. The electronic device of claim 11 wherein the doping gradient is in a range of about and including 1×10 5 to 1×10 8 centimeters cubed (cm 3 ) per cm.
13. The electronic device of claim 1 wherein the plurality of semiconductor layers further comprise one or more semiconductor layers on which the base layer is formed, and a bottom surface of the one or more semiconductor layers forms a third contact region of the electronic device.
14. The electronic device of claim 13 wherein the electronic device is a Gate Turn-Off Thyristor (GTO), and the first contact region is a gate of the GTO, the second contact region is an anode of the GTO, and the third contact region is a cathode of the GTO.
15. The electronic device of claim 13 wherein the electronic device is a Bipolar Junction Transistor (BJT), and the first contact region is a base of the BJT, the second contact region is an emitter of the BJT, and the third contact region is a collector of the BJT.
16. The electronic device of claim 1 wherein the electronic device is a MOS-Controlled Thyristor (MCT).
17. The electronic device of claim 1 wherein the interface charge is caused by crystalline damage on at least the surface of the base layer resulting from the etching of the one or more contact layers to form the second contact region.
18. The electronic device of claim 1 wherein the plurality of semiconductor layers and the semiconductor ledge layer are formed of Silicon Carbide (SiC).
19. The electronic device of claim 1 wherein the plurality of semiconductor layers and the semiconductor ledge layer are epitaxially grown semiconductor layers.