IP Library Granted Patent US 12,641,822
Granted Patent B2
US 12,641,822 · App. 16/907,163 · Granted May 26, 2026

Power devices with a hybrid gate structure

Inventors: Daniel Jenner Lichtenwalner (Raleigh, NC); Naeem Islam (Morrisville, NC)
Assignee: Wolfspeed, Inc.
H10D30/668H10D30/0297H10D64/513
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Quick Facts
Patent No.
US 12,641,822
App. No.
16/907,163
Granted
May 26, 2026
Kind
B2
Abstract

A vertical field effect device having a body, gate dielectric, and a gate electrode, which is in a trench that extends into the body from the top surface of the body and is located between first and second source regions. The first and second regions vertically overlap the gate electrode. The first and second channel regions laterally overlap a bottom of the gate electrode, such that each channel formed in the first and second source regions have a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode. In another embodiment, the first and second channel regions also vertically overlap the gate electrode such that each channel formed in the first and second source regions also have a vertical segment where the first and second channel regions vertically overlap the gate electrode.

Claims (56)

1 . A vertical field effect device comprising:

a body comprising:

a first source region and a second source region that extend into the body;

a first channel region below and laterally overlapping the first source region, the first channel region forming a first channel with a first horizontal segment that is below the first source region, and a second channel region below and laterally overlapping the second source region, the second channel region forming a second channel with a second horizontal segment that is below the second source region;

a JFET region;

a first shielding region below and laterally overlapping the first channel region, where the first shielding region directly contacts the first channel region and has a higher doping concentration than the first channel region, and a second shielding region below and laterally overlapping the second channel region, where the second shielding region directly contacts the second channel region and has a higher doping concentration than the second channel region;

a gate electrode in a trench that extends into the body and is located between the first source region and the second source region, wherein the JFET region is under the gate electrode; and

a gate dielectric between and isolating the gate electrode from the body,

wherein the first source region and the second source region vertically overlap with the gate electrode,

wherein the first channel region and the second channel region laterally overlap with a bottom of the gate electrode, and

wherein the first and second channel regions do not vertically overlap the gate electrode,

wherein the first channel region directly contacts the first source region and the second channel region directly contacts the second source region.

2 . The vertical field effect device of claim 1 wherein the first and second horizontal segments laterally overlap the bottom of the gate electrode.

3 . The vertical field effect device of claim 2 wherein the JFET region further resides between the first shielding region and the second shielding region.

4 . The vertical field effect device of claim 3 wherein the first and second channel regions are closer to one another than the first and second shielding regions, such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

5 . The vertical field effect device of claim 1 wherein no portion of the gate electrode laterally overlaps the first and second source regions.

6 . The vertical field effect device of claim 1 wherein the first and second source regions are doped with an N-type material, and the first and second channel regions are doped with a P-type material.

7 . The vertical field effect device of claim 1 wherein the field effect device is an insulated gate bipolar transistor.

8 . The vertical field effect device of claim 1 wherein the body comprises silicon carbide.

9 . The vertical field effect device of claim 1 wherein the body comprises a substrate, a drift region over the substrate, and a drain contact below the substrate, such that the JFET region is formed in an upper portion of the body above the drift region.

10 . The vertical field effect device of claim 1 wherein the trench has a depth, as measured from a top surface of the body to a bottom of the trench, between 0.2 um and 0.8 um.

11 . The vertical field effect device of claim 10 wherein the first and second shielding regions are less than two micrometers deeper than the bottom of the trench.

12 . The vertical field effect device of claim 1 wherein the field effect device is configured to block at least 300 volts in an off-state and conduct at least 1 ampere in an on-state.

13 . A vertical field effect device comprising:

a body comprising:

a first source region and a second source region that extend into the body;

a first channel region below and laterally overlapping the first source region, the first channel region forming a first channel with a first horizontal segment that is below the first source region, and a second channel region below and laterally overlapping the second source region, the second channel region forming a second channel with a second horizontal segment that is below the second source region;

a JFET region; and

a first shielding region below and laterally overlapping the first channel region, and

a second shielding region below and laterally overlapping the second channel region;

a gate electrode in a trench that extends into the body and is located laterally between the first source region and the second source region, wherein the JFET region is under the gate electrode; and

a gate dielectric between and isolating the gate electrode from the body, wherein:

the first source region and the second source region vertically overlap the gate electrode,

the first channel region and the second channel region laterally overlap a bottom of the gate electrode, and

a width of a first portion of the JFET region that is between the first channel region and the second channel region is less than a width of a second portion of the JFET region that is between the first shielding region and the second shielding region.

14 . The vertical field effect device of claim 13 wherein:

the first and second channels are formed in the first and second channel regions and where the first and second channel regions laterally overlap the bottom of the gate electrode; and

the first and second channels formed in the first and second channel regions each further have a respective vertical segment where the first and second channel regions vertically overlap the gate electrode.

15 . The vertical field effect device of claim 14 wherein the trench has a depth, as measured from a top surface of the body to a bottom of the trench, between 0.3 um and 1.3 um.

16 . The vertical field effect device of claim 15 wherein the first and second shielding regions are less than two micrometers deeper than the bottom of the trench.

17 . The vertical field effect device of claim 14 wherein the field effect device is an insulated gate bipolar transistor.

18 . The vertical field effect device of claim 14 , wherein the first and second channel regions vertically overlap sides of the gate electrode.

19 . The vertical field effect device of claim 13 wherein the body comprises silicon carbide.

20 . A vertical field effect device comprising:

a body comprising:

a first source region and a second source region;

a first channel region below and laterally overlapping the first source region, the first channel region forming a first channel with a first horizontal segment that is at least partially below the first source region, and a second channel region below and laterally overlapping the second source region, the second channel region forming a second channel with a second horizontal segment that is at least partially below the second source region;

a JFET region; and

a gate electrode in a trench that extends into the body and is located between the first source region and the second source region, the JFET region under the gate electrode;

wherein the first source region and the second source region vertically overlap with the gate electrode,

wherein the first channel region and the second channel region laterally overlap with a bottom of the gate electrode, and

wherein the first source region and the second source region each extend farther vertically into the body than does the gate electrode.

21 . The vertical field effect device of claim 20 , further comprising:

a first shielding region below and laterally overlapping the first channel region, and

a second shielding region below and laterally overlapping the second channel region.

22 . The vertical field effect device of claim 21 wherein the first shielding region directly contacts the first channel region and has a higher doping concentration than the first channel region, and the second shielding region directly contacts the second channel region and has a higher doping concentration than the second channel region.

Assignments (9)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
CHANGE OF NAME Recorded Oct 22, 2021
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 057891/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2020
From: LICHTENWALNER, DANIEL JENNER; ISLAM, NAEEM
To: CREE, INC.
Reel/Frame 052994/0867 →
Continuity (1)
Related Publication 20210399128A1 · Dec 23, 2021
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