Robust transistors with fluorine treatment
View Patent ↗A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
growing epitaxial layers on said substrate; and
introducing negative ions into said epitaxial layers to form a negative ion region to counter operating electric (E) fields in said semiconductor device and forming a gate on one of said epitaxial layers, wherein said negative ion region is arranged at least partially beyond a region below said gate.
2. The method of claim 1 , further comprising depositing contacts on said epitaxial layers.
3. The method of claim 1 , wherein said negative ions are introduced into said epitaxial layers using plasma processes in etching systems.
4. The method of claim 1 , wherein said epitaxial layers are made of Group-III nitride materials and said negative ions comprise fluorine ions.
5. A method for fabricating a high electron mobility transistor (HEMT), comprising:
providing a substrate;
growing nitride buffer and barrier layers on said substrate; and
forming a negative ion region in said barrier layer, said negative ion region countering operating electric (E) fields in said HEMT and depositing a gate on said barrier layer, wherein said negative ion region is arranged at least partially beyond a region below said gate.
6. The method of claim 5 , further comprising depositing source and drain contacts on said barrier layer.
7. The method of claim 5 , further comprising depositing source and drain contacts on said barrier layer prior to said forming of said negative ion region, and depositing said gate after said forming of said negative ion region.
8. The method of claim 5 , wherein said negative ion region comprises fluorine ions.
9. The method of claim 5 , wherein said negative ion region is formed by plasma treatment.
10. The method of claim 5 , wherein said forming said negative ion region uses plasma gas chemistry from the group CF 4 , SF 6 , and CHF 3 .
11. The method of claim 6 , wherein said negative ion region is at least partially under said gate.
12. The method of claim 1 , wherein said negative ions are introduced into said epitaxial layers using ion implantation processes.
13. The method of claim 1 , further comprising forming a drain on the one of said epitaxial layers, wherein said negative ion region extends beyond an edge of said gate toward said drain.
14. The method of claim 1 , wherein said semiconductor device comprises a high electron mobility transistor (HEMT).
15. The method of claim 1 , further comprising:
forming a first spacer layer on one of said epitaxial layers.
16. The method of claim 15 , further comprising:
forming a first field plate on said first spacer layer.
17. The method of claim 16 , further comprising:
forming a second spacer layer on said first field plate.
18. The method of claim 17 , further comprising:
forming a second field plate on said second spacer layer.
19. The method of claim 5 , further comprising depositing a drain on said barrier layer, wherein said negative ion region extends beyond an edge of said gate toward said drain.
20. The method of claim 5 wherein said buffer layer and barrier layer comprise Group-III nitride materials.
21. The method of claim 5 , wherein said negative ion region is formed by ion implantation processes.
22. A method for fabricating a semiconductor device, comprising:
growing epitaxial layers; and
introducing negative ions into said epitaxial layers to form a negative ion region to counter operating electric (E) fields in said semiconductor device and forming a gate on one of said epitaxial layers;
wherein said negative ion region is arranged at least partially beyond a region below said gate.
23. The method of claim 22 wherein said negative ion region is formed by plasma treatment.
24. The method of claim 22 , wherein said negative ion region is formed by use of ion implantation processes.
25. The method of claim 22 , further comprising forming a drain on the one of said epitaxial layers, wherein said negative ion region extends beyond an edge of said gate toward said drain.
26. The method of claim 22 , wherein said semiconductor device comprises a high electron mobility transistor (HEMT).
27. The method of claim 22 , further comprising:
forming a first spacer layer on one of said epitaxial layers.
28. The method of claim 27 , further comprising:
forming a first field plate on said first spacer layer.
29. The method of claim 28 , further comprising:
forming a second spacer layer on said first field plate.
30. The method of claim 29 , further comprising:
forming a second field plate on said second spacer layer.
31. The method of claim 22 wherein the epitaxial layers are grown on a substrate.