IP Library Patent Application 17736720
Patent Application
App. No. 17/736,720

DYNAMIC PERFORMANCE OF ON-CHIP CURRENT SENSORS

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Quick Facts
Patent No.
US None
App. No.
17/736,720
Abstract

A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce a resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed under the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.

Claims (105)

1 . A vertical semiconductor device comprising:

a drift region;

a device region that comprises a first portion of the drift region;

a sensor region that comprises a second portion of the drift region; and

a transition region between the device region and the sensor region, the transition region comprising:

a gate contact; and

a conductive segment on and in direct contact with the gate contact.

2 . The vertical semiconductor device of claim 1 , further comprising:

an insulating layer between the gate contact and the drift region; and

a gate insulating layer between the gate contact and the drift region.

3 . The vertical semiconductor device of claim 2 , wherein a thickness of the insulating layer is at least 1.5 times greater than a thickness of the gate insulating layer.

4 . The vertical semiconductor device of claim 2 , wherein a thickness of the insulating layer is in a range from 1.5 times greater to 100 times greater than a thickness of the gate insulating layer.

5 . The vertical semiconductor device of claim 2 , wherein a portion of the insulating layer has a thickness that is greater than thicknesses of other portions of the insulating layer.

6 . The vertical semiconductor device of claim 1 , wherein the sensor region comprises one or more current sensors.

7 . The vertical semiconductor device of claim 1 , wherein the first portion of the drift region is electrically connected between a first contact and a second contact and the second portion of the drift region is electrically connected between the first contact and a sensor contact.

8 . The vertical semiconductor device of claim 7 , wherein the vertical semiconductor device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), and the first contact is a drain contact and the second contact is a source contact.

9 . The vertical semiconductor device of claim 1 , further comprising:

a first isolated well region under the gate contact in the first portion of the drift region;

a second isolated well region under the gate contact in the second portion of the drift region; and

an isolation region under the gate contact in the transition region between the first and the second isolated well regions.

10 . The vertical semiconductor device of claim 9 , wherein the conductive segment and the isolation region that isolates the first and the second isolated well regions enable detection of a short circuit event in less than one microsecond of an occurrence of the short circuit event.

11 . The vertical semiconductor device of claim 9 , wherein the conductive segment and the isolation region that isolates the first isolated well region and the second isolated well region enable detection of a short circuit event within one microsecond to five microseconds of an occurrence of the short circuit event.

12 . The vertical semiconductor device of claim 1 , wherein:

the device region and the sensor region reside in an active region of the vertical semiconductor device;

the sensor region is arranged in a stripe shape and positioned along an edge of the active region;

the sensor region includes one or more current sensors; and

each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

13 . The vertical semiconductor device of claim 1 , wherein:

the device region and the sensor region reside in an active region of the vertical semiconductor device;

the sensor region is arranged in an “L” shape and a lower corner of the sensor region is positioned near a corner of the active region;

the sensor region includes one or more current sensors; and

each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

14 . A vertical semiconductor device comprising:

a drift region;

a device region that comprises a first portion of the drift region;

a sensor region that comprises a second portion of the drift region;

a transition region between the device region and the sensor region, the transition region comprising:

a gate contact over the drift region; and

an isolation region in the drift region.

15 . The vertical semiconductor device of claim 14 , further comprising a conductive segment directly on the gate contact in the transition region.

16 . The vertical semiconductor device of claim 15 , wherein the conductive segment and the isolation region enable detection of a short circuit event in less than one microsecond of an occurrence of the short circuit event.

17 . The vertical semiconductor device of claim 15 , wherein the conductive segment and the isolation region enable detection of a short circuit event within one to five microseconds of an occurrence of the short circuit event.

18 . The vertical semiconductor device of claim 14 , wherein:

the first portion of the drift region is in the device region;

the second portion of the drift region is in the sensor region;

the isolation region is an n-type isolation region;

the first isolated well region is a first p-well region; and

the second isolated well region is a second p-well region.

19 . The vertical semiconductor device of claim 14 , further comprising an insulating layer between the gate contact and the drift region.

20 . The vertical semiconductor device of claim 19 , wherein a portion of the insulating layer has a thickness that is greater than thicknesses of other portions of the insulating layer.

21 . The vertical semiconductor device of claim 14 , wherein:

the sensor region forms a current sensor; and

the vertical semiconductor device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) with the first portion of the drift region electrically connected between a drain contact and a source contact and the second portion of the drift region electrically connected between the drain contact and a sensor contact.

22 . The vertical semiconductor device of claim 14 , wherein:

the device region and the sensor region reside in an active region of the vertical semiconductor device;

the sensor region is arranged in a stripe shape and positioned along an edge of the active region;

the sensor region includes one or more current sensors; and

each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

23 . A vertical silicon carbide (SiC) device comprising:

a device region;

a sensor region; and

a transition region between the device region and the sensor region, wherein the vertical SiC device is operable to detect a short circuit event in one microsecond to three microseconds.

24 . The vertical SiC device of claim 23 , further comprising:

a conductive segment on a gate contact; and

an isolation region under the gate contact and formed in a drift region.

25 . The vertical SiC device of claim 24 , further comprising:

a well region formed in the drift region adjacent the isolation region; and

a junction field-effect transistor (JFET) region formed in the drift region adjacent the well region, wherein the isolation region is a current mirror of the JFET region.

26 . The vertical SiC device of claim 23 , wherein:

the device region and the sensor region reside in an active region of the vertical SiC device;

the sensor region is arranged in a stripe shape and positioned along an edge of the active region;

the sensor region includes one or more sensors; and

each sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more sensors in the sensor region.

27 . The vertical SiC device of claim 23 , wherein:

the device region and the sensor region reside in an active region of the vertical SiC device;

the sensor region is arranged in an “L” shape and a lower corner of the sensor region is positioned near a corner of the active region;

the sensor region includes one or more sensors; and

each sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more sensors in the sensor region.

28 . The vertical SiC device of claim 23 , wherein:

the device region is a metal-oxide-semiconductor field-effect transistor (MOSFET) device region that includes one or more MOSFET transistors; and

the sensor region is a current sensor region that includes one or more current sensors.

29 . A vertical semiconductor device, comprising:

a drift region;

a device region that comprises a first portion of the drift region; and

one or more sensor regions that each comprise a second portion of the drift region, wherein:

each sensor region includes one or more sensors; and

each sensor in a respective sensor region is at an equal distance from a respective gate contact that is electrically connected to the one or more sensors in the respective sensor region.

30 . The vertical semiconductor device of claim 29 , further comprising a transition region between the device region and a respective sensor region, the transition region comprising:

a gate contact over the drift region; and

an isolation region in the drift region.

31 . The vertical semiconductor device of claim 29 , further comprising a transition region between the device region and a respective sensor region, the transition region comprising:

a gate contact; and

a conductive segment on and in direct contact with the gate contact.

32 . The vertical semiconductor device of claim 29 , wherein:

the one or more sensor regions is a sensor region;

each sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more sensors in the sensor region; and

the one or more sensors are one or more current sensors.

33 . The vertical semiconductor device of claim 29 , wherein:

the one or more sensor regions is a first sensor region and a second region;

the first sensor region includes one or more first sensors;

each first sensor in the first sensor region is at an equal distance from a first gate contact that is electrically connected to the one or more first sensors in the first sensor region;

the second sensor region includes one or more second sensors;

each second sensor in the second sensor region is at an equal distance from a second gate contact that is electrically connected to the one or more second sensors in the second sensor region;

the one or more first sensors are one or more first current sensors; and

the one or more second sensors are one or more second current sensors.

Assignments (8)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2022
From: SAMPATH, MADANKUMAR; RYU, SEI-HYUNG; VAN BRUNT, EDWARD ROBERT
To: WOLFSPEED, INC.
Reel/Frame 059816/0506 →