Group III nitride-based monolithic microwave integrated circuits including static random access memory blocks with associated addressing and buffering circuits
A monolithic microwave integrated circuit comprises a monolithic substrate, a Group III nitride-based channel layer on the monolithic substrate, a Group III nitride-based barrier layer on the monolithic substrate, a Group III nitride-based channel layer in between the monolithic substrate and the Group III nitride-based barrier layer, a radio frequency circuit that includes a plurality of depletion mode RF transistors that are formed in the Group III nitride-based channel and barrier layers, and a static random access memory (“SRAM”) circuit that includes a SRAM block having a plurality of SRAM cells arranged in rows and columns, the SRAM circuit including a plurality of depletion mode transistors and a plurality of enhancement mode transistors that are formed in the Group III nitride-based channel and barrier layers.
1. A monolithic microwave integrated circuit, comprising:
a monolithic substrate;
a Group III nitride-based barrier layer on the monolithic substrate;
a Group III nitride-based channel layer in between the monolithic substrate and the Group III nitride-based barrier layer;
a radio frequency (“RF”) circuit that includes a plurality of depletion mode RF transistors that are formed in the Group III nitride-based channel and barrier layers; and
a static random access memory (“SRAM”) circuit that includes a SRAM block having a plurality of SRAM cells arranged in rows and columns, the SRAM circuit including a plurality of depletion mode transistors and a plurality of enhancement mode transistors that are formed in the Group III nitride-based channel and barrier layers.
2. The monolithic microwave integrated circuit of claim 1 , wherein the SRAM circuit includes a first input buffer circuit, a first column enable circuit, a first sense amplifier and a first sense amplifier buffer circuit that each include a plurality of depletion mode RF transistors and a plurality of enhancement mode RF transistors that are formed in the Group III nitride-based channel and barrier layers.
3. The monolithic microwave integrated circuit of claim 1 , wherein the first input buffer circuit, the first column enable circuit, the first sense amplifier and the first sense amplifier buffer circuit are arranged in a column that extends from a first column of SRAM cells in the SRAM block, with the first sense amplifier buffer circuit directly adjacent the first column of memory cells, and the first sense amplifier and the first column enable circuit are in between the first sense amplifier buffer circuit and the first input buffer circuit.
4. The monolithic microwave integrated circuit of claim 3 , wherein a first portion of the first column enable circuit is in between the first input buffer circuit and the first sense amplifier.
5. The monolithic microwave integrated circuit of claim 4 , wherein a second portion of the first column enable circuit is positioned within a footprint of the first sense amplifier.
6. The monolithic microwave integrated circuit of claim 3 , wherein the first input buffer circuit comprises first through eight enhancement mode transistors, each of which have respective gate electrodes that extend in a first direction, and first and second depletion mode transistors, each of which have respective gate electrodes that extend in a second direction that is perpendicular to the first direction.
7. The monolithic microwave integrated circuit of claim 6 , wherein the first through fourth enhancement mode transistors are aligned along a first axis that extends in the first direction, and wherein the fifth through eighth enhancement mode transistors are arranged to define a rectangle.
8. The monolithic microwave integrated circuit of claim 3 , wherein the first column enable circuit comprises first through third enhancement mode transistors, each of which have respective gate electrodes that extend in a first direction, and first through fourth depletion mode transistors, each of which have respective gate electrodes that extend in a second direction that is perpendicular to the first direction.
9. The monolithic microwave integrated circuit of claim 8 , wherein gate electrodes of the first through third enhancement mode transistors are aligned along a third axis that extends in the first direction.
10. The monolithic microwave integrated circuit of claim 9 , wherein the first and second depletion mode transistors are on a first side of the third axis and the third and fourth depletion mode transistors are on a second side of the third axis that is opposite the first side.
11. The monolithic microwave integrated circuit of claim 9 , wherein at least part of a first enhancement mode transistor of the first sense amplifier is positioned between the third axis and the fourth depletion mode transistor of the first column enable circuit, and at least part of a second enhancement mode transistor of the first sense amplifier is positioned between the third axis and the third depletion mode transistor of the first column enable circuit.
12. The monolithic microwave integrated circuit of claim 11 , wherein the third and fourth depletion mode transistors of the first column enable circuit are positioned between a fourth axis defined by the gate electrodes of the first and second enhancement mode transistors of the sense amplifier and a fifth axis defined by a longitudinal axis of the third enhancement mode transistor of the sense amplifier.
13. The monolithic microwave integrated circuit of claim 12 , wherein the first enhancement mode transistor of the sense amplifier is electrically coupled in series along the complementary bit line and the second enhancement mode transistor of the sense amplifier is electrically coupled in series along the bit line.
14. The monolithic microwave integrated circuit of claim 13 , wherein the first and second enhancement mode transistors of the sense amplifier are aligned along the fourth axis, and the fourth and fifth enhancement mode transistors of the sense amplifier are aligned along a sixth axis that extends in the first direction.
15. The monolithic microwave integrated circuit of claim 14 , wherein a first part of a source/drain electrode of the third enhancement mode transistor of the sense amplifier comprises a second source/drain electrode of the fourth enhancement mode transistor of the sense amplifier, and a second part of the first source/drain electrode of the third enhancement mode transistor of the sense amplifier comprises a second source/drain electrode of the fifth enhancement mode transistor of the sense amplifier.
16. The monolithic microwave integrated circuit of claim 3 , wherein the first sense amplifier buffer circuit comprises first through seventh enhancement mode transistors, each of which have respective gate electrodes that extend in a first direction, and first and second depletion mode transistors, each of which have respective gate electrodes that extend in a second direction that is perpendicular to the first direction.
17. The monolithic microwave integrated circuit of claim 16 , wherein the seventh enhancement mode transistor of the first sense amplifier buffer circuit overlaps the first through sixth enhancement mode transistors of the first sense amplifier buffer circuit in the second direction.
18. The monolithic microwave integrated circuit of claim 16 , further comprising a first pre-charge depletion mode transistor that has a gate electrode that is coupled to a gate electrode of the first enhancement mode transistor of the first sense amplifier buffer circuit and a second pre-charge depletion mode transistor that has a gate electrode that is coupled to a gate electrode of the second enhancement mode transistor of the first sense amplifier buffer circuit.
19. The monolithic microwave integrated circuit of claim 18 , wherein the first through seventh enhancement mode transistors and the first and second depletion mode transistors of the first sense amplifier buffer circuit are positioned in a region between the first bit line and the first complementary bit line, while the first pre-charge depletion mode transistor and the second pre-charge depletion mode transistor are positioned outside the region between the first bit line and the first complementary bit line.
20. The monolithic microwave integrated circuit of claim 1 , wherein a first of the SRAM cells includes first through fourth enhancement mode transistors and first and second depletion mode transistors, wherein the third and fourth enhancement mode transistors are positioned in between the first and second depletion mode transistors.
21. The monolithic microwave integrated circuit of claim 20 , wherein gate electrodes of the first through fourth enhancement mode transistors each extend in a first direction, and the first enhancement mode transistor overlaps the third enhancement mode transistor in a second direction that is perpendicular to the first direction.
22. The monolithic microwave integrated circuit of claim 21 , wherein the bit line extends between the first depletion mode transistor and the third enhancement mode transistor, and the complementary bit line extends between the second depletion mode transistor and the fourth enhancement mode transistor.
23. A monolithic microwave integrated circuit, comprising:
a monolithic substrate;
a Group III nitride-based barrier layer on the monolithic substrate;
a Group III nitride-based channel layer in between the monolithic substrate and the Group III nitride-based barrier layer; and
a static random access memory (“SRAM”) circuit that includes a SRAM block having a column of SRAM cells and a first bit line and a first complementary bit line that electrically connected to each SRAM cell in the column of SRAM cells,
wherein a first of the SRAM cells includes first through fourth enhancement mode transistors and first and second depletion mode transistors that are formed in the Group III nitride-based channel and barrier layers, and
wherein the first bit line extends between the first depletion mode transistor and the third enhancement mode transistor and the first complementary bit line extends between the second depletion mode transistor and the fourth enhancement mode transistor.
24. The monolithic microwave integrated circuit of claim 23 , wherein gate electrodes of the first through fourth enhancement mode transistors each extend in a first direction, and the first enhancement mode transistor overlaps the third enhancement mode transistor in a second direction that is perpendicular to the first direction.
25. The monolithic microwave integrated circuit of claim 24 , wherein the second enhancement mode transistor overlaps the fourth enhancement mode transistor in the second direction.
26. The monolithic microwave integrated circuit of claim 25 , wherein the first enhancement mode transistor overlaps the second enhancement mode transistor in the first direction, and the third enhancement mode transistor overlaps the fourth enhancement mode transistor in the first direction.