Power silicon carbide based MOSFET transistors with improved short circuit capabilities and methods of making such devices
A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
1. A method of forming a MOSFET, the method comprising:
providing a silicon carbide drift region that has a first conductivity type; and
implanting second conductivity type dopants into an upper portion of the silicon carbide drift region using channeled ion implantation to form first and second well regions in the upper portion of the silicon carbide drift region,
wherein an upper portion of each of the first and second well regions has the first conductivity type while a lower portion of each of the first and second well regions has the second conductivity type, the second conductivity type being different than the first conductivity type, and
wherein at least an upper 0.2 microns of the first well region has the first conductivity type.
2. The method of claim 1 , wherein the first and second well regions each have a depth of at least 1.5 microns.
3. A method of forming a MOSFET, the method comprising:
providing a silicon carbide drift region that has a first conductivity type; and
implanting second conductivity type dopants into an upper portion of the silicon carbide drift region using channeled ion implantation to form first and second well regions in the upper portion of the silicon carbide drift region,
wherein an upper portion of each of the first and second well regions has the first conductivity type while a lower portion of each of the first and second well regions has the second conductivity type, the second conductivity type being different than the first conductivity type, and
wherein a depth of the first well region exceeds a distance between the first and second well regions.
4. The method of claim 3 , wherein the first and second well regions each have a depth of at least 2.0 microns.
5. A method of forming a MOSFET, the method comprising:
providing a silicon carbide drift region that has a first conductivity type; and
implanting second conductivity type dopants into an upper portion of the silicon carbide drift region using channeled ion implantation to form first and second well regions in the upper portion of the silicon carbide drift region,
wherein an upper portion of each of the first and second well regions has the first conductivity type while a lower portion of each of the first and second well regions has the second conductivity type, the second conductivity type being different than the first conductivity type, and
wherein a side portion of the first well region that is underneath a gate electrode of the MOSFET comprises a channel region, and wherein at least a portion of the channel region has the first conductivity type.
6. The method of claim 5 , wherein the channel region is formed using channeled ion implantation.
7. The method of claim 5 , wherein the channel region and a central portion of the first well region have substantially the same doping profile of second conductivity type dopants as a function of depth from an upper surface of the silicon carbide drift region.
8. The method of claim 1 , wherein the channeled ion implantation implants dopant impurities at an angle that is within +1-1.5° of one of the <0001>, <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide drift region.
9. A method of forming a MOSFET, the method comprising:
forming a silicon carbide drift region having a first conductivity type;
forming a first well region located in an upper portion of the silicon carbide drift region and extending to an upper surface of the silicon carbide drift region, the first well region doped with second conductivity type dopants and at least a lower portion of the first well region having a second conductivity type, wherein the second conductivity type is different than the first conductivity type, and wherein the first well region comprises a channel region having the first conductivity type in an upper portion of the channel region;
forming a second well region in the upper portion of the silicon carbide drift region and extending to the upper surface of the silicon carbide drift region, the second well region doped with the second conductivity type dopants and at least a lower portion of the second well region having the second conductivity type, the first and second well regions defining a JFET region therebetween; and
forming a gate insulating layer on the upper portion of the channel region,
wherein a doping density of the silicon carbide drift region, a width of the JFET region, a doping density of the channel region, and/or a depth of the first well region are selected to produce a negative temperature coefficient for a drain current for at least temperatures in a range of 25−150° C. at drain-source currents of less than 40 Amps.
10. The method of claim 9 , wherein the depth of the first well region is at least 1.5 microns, and wherein the depth of the first well region exceeds a distance between the first well region and the second well region.
11. The method of claim 9 , wherein at least an upper 0.2 microns of the first well region has the first conductivity type.
12. The method of claim 9 , wherein the channel region and a central portion of the first well region have a substantially same doping profile of the second conductivity type dopants as a function of depth from the upper surface of the silicon carbide drift region.
13. The method of claim 9 , wherein forming the first well region comprises performing a channeled ion implantation at an angle that is within +1-1.5° of one of the <0001>, <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide drift region.
14. The method of claim 9 , wherein the channel region is formed using channeled ion implantation.
15. The method of claim 9 , wherein a concentration of second conductivity type dopants in the first well region varies by less than a factor of three at depths between 1.0 and 2.0 microns from the upper surface of the silicon carbide drift region.
16. The method of claim 9 , wherein a lower portion of the channel region has the second conductivity type.
17. The method of claim 1 , wherein a concentration of second conductivity type dopants in the first well region varies by less than a factor of three at depths between 1.0 and 2.0 microns from an upper surface of the silicon carbide drift region.
18. The method of claim 5 , wherein an upper portion of the channel region has the first conductivity type and a lower portion of the channel region has the second conductivity type.
19. The method of claim 3 , wherein the first and second well regions each have a depth of at least 1.5 microns.
20. The method of claim 3 , wherein the channeled ion implantation implants dopant impurities at an angle that is within +1-1.5° of one of the <0001>, <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide drift region.