Semiconductor device with improved short circuit withstand time and methods for manufacturing the same
A semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has the first conductivity type and is on the substrate. The well region has a second conductivity type opposite the first conductivity type and provides a channel region. The source region is in the well region and has the first conductivity type. A doping concentration of the well region along a surface of the drift layer opposite the substrate is variable such that the well region includes a region of increased doping concentration at a distance from a junction between the source region and the well region.
1. A semiconductor device comprising:
a substrate, the substrate having a first conductivity type;
a drift layer on the substrate, the drift layer having the first conductivity type;
a well region in the drift layer, wherein:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
a source region in the well region, wherein:
the well region is between the source region and the drift layer;
the source region has the first conductivity type; and
the channel region comprises a first region of increased doping concentration at a surface of the drift layer opposite the substrate, and the first region is laterally separated from the source region along the surface of the drift layer by a second region having a laterally constant doping concentration that is lower than the increased doping concentration of the first region.
2. The semiconductor device of claim 1 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate increases in proportion to a distance between an interface between the source region and the well region such that the increase in doping concentration is towards an interface between the well region and the drift region along the surface of the drift region opposite the substrate.
3. The semiconductor device of claim 1 wherein the first region is located along an interface between the well region and the drift region.
4. The semiconductor device of claim 3 wherein a doping concentration of the first region is between 1.1 and 250 times greater than a doping concentration of the remainder of the well region.
5. The semiconductor device of claim 4 wherein the doping concentration of the first region is between 2×10 17 and 5×10 19 cm −3 .
6. The semiconductor device of claim 5 wherein a doping concentration of the second region is between 5×10 15 and 5×10 17 cm 3 .
7. The semiconductor device of claim 3 wherein a distance between the first region and an interface between the source region and the well region is between 0.2 and 2 μm.
8. The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in a linear fashion.
9. The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in a stepwise fashion.
10. The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in an exponential fashion.
11. The semiconductor device of claim 1 wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).
12. The semiconductor device of claim 11 further comprising:
a drain contact on a surface of the substrate opposite the drift layer;
a source contact on the surface of the drift layer opposite the substrate such that the source contact is in contact with the source region and the well region;
a gate oxide on the surface of the drift layer opposite the substrate such that the gate oxide is in contact with the well region and the source region and separated from the source contact, wherein the channel region of the MOSFET is below the gate oxide in the well region; and
a gate contact on the gate oxide.
13. The semiconductor device of claim 1 wherein a depth of the source region is non-uniform.
14. The semiconductor device of claim 13 wherein the depth of the source region increases in proportion to a distance from the channel region.
15. A semiconductor device comprising:
a substrate, the substrate having a first conductivity type;
a drift layer on the substrate, the drift layer having the first conductivity type;
a well region in the drift layer, wherein:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
a source region in the well region, wherein:
the well region is between the source region and the drift layer;
the source region has the first conductivity type;
the source region comprises a first region of decreased depth compared to a second region of the source region; and
a doping concentration of the source region remains constant across the first region and the second region.
16. The semiconductor device of claim 15 wherein a depth of the source region increases in proportion to a distance from the channel region.
17. The semiconductor device of claim 16 wherein the depth of the source region at a first edge of the source region nearest the channel region is between 0.06 and 0.93 times less than the depth of the source region at a second edge of the source region opposite the first edge.
18. The semiconductor device of claim 16 wherein the depth of the source region varies in a linear fashion.
19. The semiconductor device of claim 16 wherein the depth of the source region varies in a stepwise fashion.
20. The semiconductor device of claim 15 , wherein the channel region comprises a first region of increased doping concentration at a surface of the drift layer opposite the substrate, and the first region is laterally separated from the source region along the surface of the drift layer by a second region having a laterally constant doping concentration.
21. A method for manufacturing a semiconductor device comprising:
providing a substrate having a first conductivity type;
providing a drift layer on the substrate, the drift layer having the first conductivity type;
providing a well region in the drift layer such that:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
providing a source region in the well region such that:
the well region is between the source region and the drift layer;
the source region has the first conductivity type; and
the channel region comprises a first region of increased doping concentration at a distance from a junction between the source region and the well region, and the first region is laterally separated from the source region along a lateral surface of the drift layer opposite the substrate by a second region having a laterally constant doping concentration that is lower than the increased doping concentration of the first region.
22. The method of claim 21 wherein the well region is provided such that a doping concentration of the first region is between 1.1 and 250 times greater than a doping concentration of the second region.
23. The method of claim 21 wherein a doping concentration of the first region is between 2×10 17 and 5×10 19 cm −3 .
24. The method of claim 23 wherein a doping concentration of the second region is between 5×10 15 and 5×10 17 cm −3 .
25. The method of claim 21 wherein the distance between the first region of increased doping concentration and the junction between the source region and the well region is between 0.2 and 2 μm.
26. The method of claim 21 wherein:
providing the well region comprises providing a well implantation mask on the drift layer and performing an ion implantation process; and
providing the source region comprises providing a source implantation mask on the drift layer and performing an ion implantation process.
27. The method of claim 26 wherein providing the drift layer comprises growing the drift layer via an epitaxy process.