IP Library Granted Patent US 7,719,025
Granted Patent B2
US 7,719,025 · App. 11/550,650 · Granted May 18, 2010

Integrated circuit ESD protection

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Quick Facts
Patent No.
US 7,719,025
App. No.
11/550,650
Granted
May 18, 2010
Kind
B2
Abstract

A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of the first conductivity type extending from the top surface into the body area, an isolation area surrounding the first area, a ring area of the first conductivity type surrounding the isolation area, and a coupling structure for connecting the ring area with the substrate.

Claims (44)

1. A protective device in a semiconductor comprising:

a substrate of a first conductivity type,

an epitaxial layer formed on top of said substrate,

a body area of a second conductivity type formed within said epitaxial layer and extending from a top surface into said epitaxial layer,

a first area of the first conductivity type extending from said top surface into said body area,

an isolation area surrounding said first area,

a ring area of the first conductivity type surrounding said isolation area,

a coupling structure for electrically connecting said ring area with said substrate.

2. A protective device according to claim 1 , further comprising

a first intermediate ring area of said first conductivity type arranged between said first area and said isolation area, and

a second intermediate ring area of said first conductivity type arranged between said isolation area and said ring area.

3. A protective device according to claim 2 , wherein the first and second intermediate areas are less doped than the first area.

4. A protective device according to claim 2 , wherein said first area and said ring area extend from said top surface deeper into said epitaxial layer than said first and second intermediate areas.

5. A protective device according to claim 1 , wherein said isolation area is formed by local oxidation of silicon or other isolation methods.

6. A protective device according to claim 1 , wherein said body area extends to a top surface of said substrate.

7. A protective device according to claim 1 , wherein said body area is embedded into said epitaxial layer in such a way that the epitaxial layer surrounds said body area with a cup-shaped form.

8. A protective device according to claim 1 , wherein said first area has a circular, square, octagonal, or polygonal shape.

9. A protective device according to claim 1 , wherein said isolation area and said ring area have a circular, square, octagonal, or polygonal shape.

10. A protective device according to claim 1 , wherein said coupling structure is a sinker of said first conductivity type.

11. A protective device according to claim 10 , wherein said sinker is adjacent to said ring area and reaches from said top surface to the substrate.

12. A protective device according to claim 10 , wherein said sinker is arranged below said ring area and reaches from a bottom of said ring area to the substrate.

13. A protective device according to claim 1 , wherein said coupling structure is a trench structure filled with a conductive material.

14. A protective device according to claim 13 , further comprising metal barrier layers between said trench structure and said ring area and said substrate, respectively.

15. A protective device according to claim 1 , further comprising an LDMOS transistor having a gate, wherein said gate is electrically connected with said first area.

16. A protective device according to claim 15 , wherein said LDMOS transistor comprises a source zone being adjacent and connected to said coupling structure.

17. A protective device in a semiconductor comprising:

a substrate of a first conductivity type,

an epitaxial layer formed on top of said substrate,

a body area of a second conductivity type formed within said epitaxial layer and extending from a top surface into said epitaxial layer,

a first area of the first conductivity type extending from said top surface into said body area,

a first ring area of the first conductivity type surrounding said first area,

an isolation area surrounding said first ring area,

a second ring area of the first conductivity type surrounding said isolation area,

a third ring area of the first conductivity type surrounding said second ring area,

a coupling structure for connecting said third ring area with said substrate.

18. A protective device according to claim 17 , wherein the first and second ring areas are less doped than the first area.

19. A protective device according to claim 17 , wherein said first area and said third ring area extend from said top surface deeper into said epitaxial layer than said first and second ring areas.

20. A protective device according to claim 17 , wherein said isolation area is formed by local oxidation of silicon or other isolation methods.

21. A protective device according to claim 17 , wherein said body area extends to a top surface of said substrate.

22. A protective device according to claim 17 , wherein said first area has a circular, square, octagonal, or polygonal shape.

23. A protective device according to claim 17 , wherein said isolation area and said first and second ring area have a circular, square, octagonal, or polygonal shape.

24. A protective device according to claim 17 , wherein said coupling structure is a sinker of said first conductivity type.

25. A protective device according to claim 24 , wherein said sinker is adjacent to said third ring area and reaches from said top surface to the substrate.

26. A protective device according to claim 24 , wherein said sinker is arranged below said third ring area and reaches from a bottom of said third ring area to the substrate.

Assignments (8)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
CHANGE OF NAME Recorded Feb 14, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 059085/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2018
From: INFINEON TECHNOLOGIES AG
To: CREE, INC.
Reel/Frame 045870/0504 →