Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices
A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.
1. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide;
a gate dielectric layer on the semiconductor layer structure; and
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure,
wherein a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer,
wherein a lower surface of the gate electrode has recessed outer edges, and
wherein a periphery of an upper surface of the gate electrode is recessed.
2. The semiconductor device of claim 1 , wherein each recessed outer edge of the gate electrode includes multiple beveled or rounded regions.
3. The semiconductor device of claim 1 , wherein a lower surface of the gate dielectric layer is substantially flat.
4. The semiconductor device of claim 1 , wherein the semiconductor layer structure includes a drift layer having a first conductivity type, a well having a second conductivity type that is opposite the first conductivity type in an upper portion of the drift layer, and a source region having the first conductivity type in the well, wherein the source region is formed via ion implantation, and wherein a concentration of dopants in an upper portion of the source region is selected so that a predetermined portion of the upper portion of the source region will be converted to dielectric material during the formation of the gate dielectric layer.
5. The semiconductor device of claim 3 , wherein the semiconductor layer structure includes a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer and a source region having the first conductivity type in an upper portion of the well, and
wherein a channel region is provided in the well between the source region and a portion of the drift layer that contacts the gate dielectric layer.
6. The semiconductor device of claim 3 , wherein the recessed outer edges of the lower surface of the gate electrode comprise rounded edges.
7. The semiconductor device of claim 3 , wherein a central portion of the gate electrode extends farther above the semiconductor layer structure than does a periphery of the upper surface of the gate electrode.
8. The semiconductor device of claim 5 , wherein a portion of the gate dielectric layer beneath the gate electrode that overlies the source region is thicker than a portion of the gate dielectric layer that overlies the channel region.
9. The semiconductor device of claim 5 , wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer will be located substantially above a sidewall of the channel region that contacts the source region.
10. The semiconductor device of claim 5 , wherein the source region is in a central portion of the well, and wherein an upper surface of a portion of the well on a first side of the source region extends farther above the drift layer than does an upper surface of the source region, and an upper surface of a portion of the well on a second side of the source region that is opposite the first side also extends farther above the drift layer than does the upper surface of the source region.
11. The semiconductor device of claim 5 , wherein an upper surface of the well extends farther above the drift layer than does an upper surface of the source region.
12. A semiconductor device, comprising:
a semiconductor layer structure that includes silicon carbide, the semiconductor layer structure including a drift layer having a first conductivity type, a well having a second conductivity type that is opposite the first conductivity type in an upper portion of the drift layer, and a source region having the first conductivity type in the well;
a trench in the semiconductor layer structure;
a gate dielectric layer in the trench; and
a gate electrode in the trench on the gate dielectric layer,
wherein an upper surface of the gate electrode has recessed outer edges.
13. The semiconductor device of claim 12 , wherein a location in the gate dielectric layer where a peak electric field value occurs is spaced inwardly from a sidewall of the gate electrode.
14. The semiconductor device of claim 12 , wherein the recessed outer edges of the upper surface of the gate electrode are rounded edges.
15. The semiconductor device of claim 12 , wherein a central portion of the gate electrode extends farther above the semiconductor layer structure than does a periphery of the upper surface of the gate electrode.
16. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide;
a gate dielectric layer on an upper surface of the semiconductor layer structure; and
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure,
wherein a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer,
wherein a lower surface of the gate electrode has recessed outer edges,
wherein the semiconductor layer structure includes a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer and a source region having the first conductivity type in an upper portion of the well,
wherein a channel region is provided in the well between the source region and a portion of the drift layer that contacts the gate dielectric layer, and
wherein an upper surface of the well extends farther above a bottom surface of the semiconductor device than does an upper surface of the source region.
17. The semiconductor device of claim 16 , wherein the gate electrode is at least partially within a trench in the semiconductor layer structure.
18. The semiconductor device of claim 17 , wherein an upper surface of the gate electrode has recessed outer edges.
19. The semiconductor device of claim 16 , wherein the recessed outer edges of the lower surface of the gate electrode are rounded outer edges.
20. The semiconductor device of claim 16 , wherein the gate dielectric layer extends laterally on the semiconductor layer structure beyond a first sidewall of the gate electrode and beyond a second sidewall of the gate electrode.