DIFFUSION AND/OR ENHANCEMENT LAYERS FOR ELECTRICAL CONTACT REGIONS
Power switching devices include a semiconductor layer structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.
1 . A semiconductor device comprising:
a semiconductor layer structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad;
an isolation layer between the gate pad and the gate bond pad; and
a barrier layer between the gate pad and the isolation layer.
2 . The semiconductor device of claim 1 , wherein the barrier layer is a first barrier layer, the semiconductor device further comprising:
a second barrier layer on the gate pad and on the first barrier layer,
wherein at least a portion of the isolation layer is between the first barrier layer and the second barrier layer.
3 - 4 . (canceled)
5 . The semiconductor device of claim 1 , wherein the barrier layer comprises titanium (Ti) and/or tantalum (Ta).
6 . The semiconductor device of claim 1 , wherein the barrier layer is on a top surface and a sidewall of the gate pad.
7 . The semiconductor device of claim 1 , wherein the barrier layer is a first barrier layer, the semiconductor device further comprising:
a gate finger on the active region and electrically connected to the gate bond pad; and
a second barrier layer on the gate finger.
8 . The semiconductor device of claim 7 , wherein the second barrier layer is on a top surface and a sidewall of the gate finger.
9 . The semiconductor device of claim 1 , wherein the barrier layer is a first barrier layer, the semiconductor device further comprising:
a source contact on the semiconductor layer structure;
a second barrier layer on sidewalls and a bottom surface of the source contact; and
a third barrier layer between the semiconductor layer structure and the second barrier layer.
10 . A semiconductor device comprising:
a semiconductor substrate;
a gate pad on the semiconductor substrate;
a gate bond pad on and electrically connected to the gate pad;
a first barrier layer between a bottom portion of gate bond pad and the gate pad in a first direction perpendicular to a top surface of the semiconductor substrate; and
a second barrier layer between the gate pad and the first barrier layer in the first direction.
11 . The semiconductor device of claim 10 , wherein the second barrier layer has a width in a second direction that is parallel to a top surface of the semiconductor substrate that exceeds that of a portion of the first barrier layer that is between the second barrier layer and a bottom portion of the gate bond pad.
12 . The semiconductor device of claim 11 , wherein a thickness of the second barrier layer is substantially uniform along the width of the second barrier layer in the second direction.
13 . The semiconductor device of claim 10 , wherein the gate bond pad is coupled to the gate pad via a contact hole having opposing sidewalls,
wherein a portion of the first barrier layer is on the opposing sidewalls of the contact hole, and
wherein a width of the second barrier layer in a second direction that is parallel to a top surface of the semiconductor substrate is greater than a width of the contact hole in the second direction.
14 . The semiconductor device of claim 10 , further comprising an isolation layer, wherein a portion of the isolation layer is between the second barrier layer and the gate bond pad.
15 - 16 . (canceled)
17 . The semiconductor device of claim 10 , wherein the second barrier layer is on a top surface and a sidewall of the gate pad.
18 . The semiconductor device of claim 10 , wherein a material of the second barrier layer is different from a material of the first barrier layer.
19 . The semiconductor device of claim 10 , further comprising:
a semiconductor layer structure comprising an active region and an inactive region, wherein the gate pad is on the inactive region;
a gate finger on the active region and electrically connected to the gate pad; and
a third barrier layer on the gate finger.
20 . The semiconductor device of claim 19 , wherein the third barrier layer is on a top surface and a sidewall of the gate finger.
21 - 24 . (canceled)
25 . A semiconductor device, comprising:
a semiconductor layer structure;
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on a top surface of the semiconductor layer structure, the gate fingers spaced apart from each other along a second direction; and
an auxiliary gate electrode barrier layer on an upper surface of each of the gate fingers.
26 . The semiconductor device of claim 25 , wherein the gate finger comprises polysilicon.
27 . (canceled)
28 . The semiconductor device of claim 25 , wherein the auxiliary gate electrode barrier layer is also on opposing sidewalls of each of the gate fingers.
29 . The semiconductor device of claim 25 , wherein the semiconductor layer structure comprises an inactive region and an active region,
wherein the active region comprises the plurality of unit cell transistors, and
wherein the inactive region comprises:
a gate pad on the semiconductor layer structure;
a gate bond pad on and electrically connected to the gate pad;
an isolation layer between the gate pad and the gate bond pad; and
an auxiliary gate pad barrier layer between the gate pad and the isolation layer.
30 . (canceled)
31 . The semiconductor device of claim 29 , further comprising a gate pad barrier layer between the auxiliary gate pad barrier layer and the gate bond pad.
32 . (canceled)
33 . The semiconductor device of claim 25 , further comprising:
a source contact on the semiconductor layer structure;
a source barrier layer on sidewalls and a bottom surface of the source contact; and
an auxiliary source barrier layer between the semiconductor layer structure and the source barrier layer.
34 . The semiconductor device of claim 25 , further comprising an isolation layer on the gate finger,
wherein the auxiliary gate electrode barrier layer is between the isolation layer and the gate finger.