Silicon carbide self-aligned epitaxial MOSFET for high powered device applications
A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
1. A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
at least two oxide spacers on the second epitaxial layer;
a source contact between the oxide spacers and in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer that is over the trench that is not between the oxide spacers;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.
2. The MOSFET of claim 1 , further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.
3. The MOSFET of claim 1 , wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.
4. The MOSFET of claim 1 , wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.
5. The MOSFET of claim 1 , wherein the first layer and the first and second epitaxial layers are silicon carbide.
6. The MOSFET of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
7. A device comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface toward the second surface, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
at least two oxide spacers on the second epitaxial layer;
a source contact between the oxide spacers and in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.
8. The device of claim 7 , further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.
9. The device of claim 7 , wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.
10. The device of claim 7 , wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.
11. The device of claim 7 , wherein the first layer and the first and second epitaxial layers are silicon carbide.
12. The device of claim 7 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
13. A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
oxide spacers over the trench on the second epitaxial layer;
a source contact within the trench between and in direct contact with the oxide spacers, and also in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.
14. The MOSFET of claim 13 , further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.
15. The MOSFET of claim 13 , wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.
16. The MOSFET of claim 13 , wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.
17. The MOSFET of claim 13 , wherein the first layer and the first and second epitaxial layers are silicon carbide.
18. The MOSFET of claim 13 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
19. A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
an epitaxial base layer within the trench on sidewalls and a bottom of the trench, the epitaxial base layer having a second conductivity type opposite the first conductivity type;
an epitaxial source layer within the trench on the epitaxial base layer and extending out of and over the trench, the epitaxial source layer having the first conductivity type;
oxide spacers on the epitaxial source layer and extending out of and over the trench;
a source contact within the trench between the oxide spacers and in contact with the epitaxial base and source layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the epitaxial base layer;
a gate electrode on the gate oxide layer over the surface of the epitaxial base layer; and
a drain electrode over the second surface of the first layer.
20. The MOSFET of claim 19 , further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the epitaxial base layer.
21. The MOSFET of claim 19 , wherein the epitaxial base layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the epitaxial base layer.
22. The MOSFET of claim 19 , wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.
23. The MOSFET of claim 19 , wherein the first layer and the epitaxial base and source layers are silicon carbide.
24. The MOSFET of claim 19 , wherein the first conductivity type is n-type and the second conductivity type is p-type.