Robust transistors with fluorine treatment
View Patent ↗A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
1. A transistor, comprising:
a plurality of semiconductor layers;
a gate on a surface of said semiconductor layers; and
a negative ion region in said semiconductor layers, wherein said negative ion region is arranged beneath said gate and extends out laterally beyond an edge of said gate.
2. The transistor of claim 1 , wherein said semiconductor layers comprise a buffer layer and a barrier layer on said buffer layer.
3. The transistor of claim 2 , wherein said negative ion region is in said barrier layer.
4. The transistor of claim 2 , wherein said negative ion region is in said barrier layer and said buffer layer.
5. The transistor of claim 2 , further comprising a two dimensional electron gas (2DEG) at the interface between said buffer layer and said barrier layer.
6. The transistor of claim 1 , further comprising source and drain contacts on said semiconductor layers.
7. The transistor of claim 1 , wherein said buffer and barrier layers are made of Group-III nitride materials.
8. The transistor of claim 1 , wherein said negative ion region comprises fluorine ions.
9. The transistor of claim 1 , wherein said negative ion region is positioned to counter and reduce the transistor's operating electric (E) field.
10. The transistor of claim 1 , wherein said negative ion region is arranged to oppose the positive charge resulting from polarization between semiconductor layers.
11. The transistor of claim 6 , wherein said negative ion region is below said gate.
12. The transistor of claim 1 , wherein said negative ion region has different depths in said barrier layer.
13. The transistor of claim 1 , wherein said negative ion region comprises different concentrations of negative ions at different locations.
14. The transistor of claim 1 , further comprising a field plate.
15. A semiconductor based device, comprising:
a plurality of active semiconductor layers experiencing an operating electric (E) field;
a gate on said semiconductor layers; and
a negative ion region within at least one of said plurality of semiconductor layers and arranged at the surface of said semiconductor layers or below said gate to counter said operating (E) field, said negative ion region arranged beneath said gate and extending out laterally beyond an edge of said gate.
16. The semiconductor device of claim 15 , comprising a transistor.
17. The semiconductor device of claim 15 , comprising a high electron mobility transistor (HEMT).
18. The semiconductor device of claim 15 , wherein said active semiconductor layers comprise Group-III nitride materials.
19. The semiconductor device of claim 15 , wherein said negative ion region comprises fluorine ions.
20. The semiconductor device of claim 15 , wherein said negative ion region has sections with different depths in said active semiconductor layers.
21. The semiconductor device of claim 15 , wherein said negative ion region comprises different concentrations of negative ions at different locations.
22. A transistor, comprising:
a plurality of semiconductor layers;
a gate on a surface of said semiconductor layers;
a negative ion region in said semiconductor layers and below said gate; and
a first field plate,
wherein said negative ion region is arranged beneath said gate and extends out laterally beyond an edge of said gate beneath said field plate.
23. The transistor of claim 22 , further comprising a spacer layer on said semiconductor layers, said first field plate on said spacer layer.
24. The transistor of claim 23 , wherein said first field plate is integral to said gate.
25. The transistor of claim 22 , wherein said first field plate is electrically connected to said gate.
26. The transistor of claim 22 , further comprising source and drain electrodes, wherein said first field plate extends from said gate toward said drain electrode.
27. The transistor of claim 22 , further comprising a second spacer layer and a second field plate on said second spacer layer.
28. The transistor of claim 27 , wherein said second field plate overlaps said first field plate.