IP Library Granted Patent US 12,279,448
Granted Patent B2
US 12,279,448 · App. 17/831,599 · Granted Apr 15, 2025

Trench bottom shielding methods and approaches for trenched semiconductor device structures

Inventors: Woongsun Kim (Cary, NC); Daniel J. Lichtenwalner (Raleigh, NC); Naeem Islam (Morrisville, NC); Sei-Hyung Ryu (Cary, NC)
Assignee: Wolfspeed, Inc.
H10D30/668H10D30/021H10D64/252H10D64/518
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Quick Facts
Patent No.
US 12,279,448
App. No.
17/831,599
Granted
Apr 15, 2025
Kind
B2
Abstract

Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Claims (32)

1. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type;

a plurality of trenches in an upper portion of the wide band-gap semiconductor layer structure, each trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening, and the plurality of trenches comprising source trenches and gate trenches;

a polysilicon layer in a bottom of at least some of the source trenches and in direct contact with the drift region; and

a plurality of gate electrodes, each gate electrode arranged within a respective gate trench.

2. The device of claim 1 , wherein each of the source trenches includes the polysilicon layer.

3. The device of claim 2 , wherein each source trench extends in length in a direction parallel to an upper surface of the wide band-gap semiconductor layer structure, and wherein each polysilicon layer extends the length of the respective source trench.

4. The device of claim 1 , wherein each source trench and each gate trench extends in length in a direction parallel to an upper surface of the wide band-gap semiconductor layer structure.

5. The device of claim 1 , further comprising channel regions on the first sidewall of the gate trenches, wherein the wide band-gap semiconductor layer structure comprises well regions having a second conductivity type that is different from the first conductivity type, and wherein the channel regions are in the well regions.

6. The device of claim 1 , wherein at least one gate trench has an oxide layer therein.

7. The device of claim 1 , wherein the wide band-gap semiconductor layer structure comprises silicon carbide.

8. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type;

a plurality of gate trenches in an upper portion of the wide band-gap semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternately arranged in a direction parallel to an upper surface of the wide band-gap semiconductor layer structure; and

a plurality of polysilicon layers, wherein each polysilicon layer is on both the first and second sidewalls of a respective first length portion of the plurality of gate trenches;

wherein the first and second sidewalls of the second length portions of the plurality of gate trenches are free from the polysilicon layers.

9. The device of claim 8 , further comprising an oxide layer within each gate trench.

10. The device of claim 9 , wherein the oxide layer comprises a first cross-section in the first length portions of each gate trench and a second cross-section in the second length portions of each gate trench.

11. The device of claim 8 , further comprising a gate structure within respective gate trenches, wherein the gate structure comprises a gate electrode.

12. The device of claim 11 , wherein the gate electrode comprises a first cross-section in the first length portions of each gate trench, and a second cross-section in the second length portions of each gate trench.

13. The device of claim 8 , wherein the wide band-gap semiconductor layer structure comprises well regions having a second conductivity type that is different from the first conductivity type.

14. The device of claim 8 , further comprising a first source/drain contact on a first major surface of the wide band-gap semiconductor layer structure and a second source/drain contact on a second major surface of the wide band-gap semiconductor layer structure opposite from the first major surface.

15. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type, a well region that has a second conductivity type that is different from the first conductivity type, and a source region that has the first conductivity type;

a plurality of gate trenches in an upper portion of the wide band-gap semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening, and each gate trench exposing side surfaces of the drift region; and

a source contact that is electrically connected to the source region;

a plurality of polysilicon layers, each polysilicon layer on portions of at least one of the first and second sidewalls of a respective gate trench and having an upper surface above the wide band-gap semiconductor layer structure,

wherein the plurality of polysilicon layers are electrically connected to the source contact.

16. The device of claim 15 , wherein each gate trench has first length portions and second length portions, and wherein each polysilicon layer covers an entirety of the second sidewall within a first of the second length portions of the respective gate trench.

17. The device of claim 16 , wherein each polysilicon layer covers an entirety of the first sidewall within the first of the second length portions of the respective gate trench.

18. The device of claim 15 , wherein each polysilicon layer extends longitudinally and covers portions of each of the first and second sidewalls along a length of the respective gate trench.

19. The device of claim 15 , further comprising a gate structure within respective gate trenches, wherein the gate structure comprises a gate electrode.

Assignments (7)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →