Gate trench power semiconductor devices having trench shielding patterns formed during the well implant and related methods
A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.
1 . A method of fabricating a semiconductor device, the method comprising:
providing a wide band-gap semiconductor layer structure that comprises a drift region having a first conductivity type and a source region having the first conductivity type on the drift region, the wide band-gap semiconductor layer structure comprising a trench therein; and
implanting second conductivity type dopants into the wide band-gap semiconductor layer structure to simultaneously form both a well region underneath the source region and a trench shielding region underneath the trench, the well region and the trench shielding region each having a second conductivity type.
2 . The method of claim 1 , wherein the trench comprises a gate trench that extends through the source region and into the drift region.
3 . The method of claim 1 , wherein implanting second conductivity type dopants into the wide band-gap semiconductor layer structure comprises implanting the second conductivity type dopants through the source region into the drift region.
4 . The method of claim 1 , wherein the well region is formed by converting a portion of the drift region having the first conductivity type into the well region having the second conductivity type.
5 . The method of claim 1 , wherein the well region separates the source region from the drift region.
6 . The method of claim 1 , wherein the source region forms an upper portion of both a first sidewall and a second sidewall of the trench and the drift region forms a lower portion of the first sidewall and the second sidewall, wherein the first sidewall faces the second sidewall.
7 . The method of claim 6 , wherein an entirety of the first sidewall of the trench is exposed when the second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure.
8 . The method of claim 7 , the method further comprising:
performing an oxidation process to convert at least the first and second sidewalls and a bottom of the trench into an oxide material; and
removing the oxide material to convert the trench into an enlarged trench.
9 . The method of claim 1 , wherein the wide band-gap semiconductor layer structure extends in a length direction, a width direction and a depth direction that are perpendicular to each other, and a lower surface of the wide band-gap semiconductor layer structure extends in the length and width directions, wherein the source region extends a first distance in the depth direction and the trench shielding region extends a second distance in the depth direction, where the second distance is at least twice the first distance.
10 . The method of claim 1 , wherein a concentration of second conductivity type dopants in the source region is at least 5×10 15 /cm 3 .
11 . The method of claim 1 , wherein a doping profile of a lower portion of the trench shielding region that is taken along a first axis that extends in the depth direction through a center of the bottom of the gate trench varies by less than 15% from a doping profile of the well region that is taken along a second axis that is parallel to the first axis and that extends through the well region.
12 . The method of claim 1 , the method further comprising implanting additional second conductivity type dopants into the wide band-gap semiconductor layer structure underneath the trench via a different ion implantation process than an ion implantation process used to simultaneously form both the well region underneath the source region and the trench shielding region underneath the trench, where the different ion implantation process has a lower implantation energy than the ion implantation process used to simultaneously form both the well region underneath the source region and the trench shielding region underneath the trench.
13 . The method of claim 12 , wherein the second conductivity type dopants and the additional second conductivity type dopants are implanted using a same ion implantation mask.
14 . The method of claim 12 , wherein the additional second conductivity type dopants are implanted before the second conductivity type dopants are implanted.
15 . The method of claim 12 , the method further comprising forming a mask on sidewalls of the trench before implanting the additional second conductivity type dopants into the wide band-gap semiconductor layer structure.
16 . The method of claim 12 , wherein an upper surface of the source region is exposed when the additional second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure.
17 . The method of claim 8 , the method further comprising implanting additional second conductivity type dopants into the wide band-gap semiconductor layer structure underneath the trench after the source region is formed.
18 . The method of claim 12 , wherein the additional second conductivity type dopants are implanted before an oxidation process is performed to convert at least the first and second sidewalls and a bottom of the trench into an oxide material.
19 . The method of claim 1 , wherein an upper surface of the source region is exposed when the second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure.
20 . The method of claim 2 , wherein the trench shielding region extends the full length of the gate trench.
21 . A method of fabricating a semiconductor device, the method comprising:
providing a wide band-gap semiconductor layer structure that comprises a drift region having a first conductivity type and a source region having the first conductivity type on the drift region; and then
forming a gate trench in the wide band-gap semiconductor layer structure; and then
performing a first ion implantation process to form a well region having a second conductivity type in the semiconductor layer structure directly underneath the source region.
22 . The method of claim 21 , wherein performing the first ion implantation process to form the well region having the second conductivity type in the semiconductor layer structure directly underneath the source region comprises implanting second conductivity dopants so that they penetrate through the source region to form the well region directly underneath the source region.
23 . A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor layer structure that comprises a drift region having a first conductivity type and a source region having the first conductivity type on the drift region;
forming a gate trench in the semiconductor layer structure; and then
forming both (1) a well region having a second conductivity type underneath the source region and (2) a trench shielding region having the second conductivity type underneath the gate trench.
24 . The method of claim 23 , wherein the well region is formed by implanting second conductivity type dopants so that they penetrate through the source region.
25 . The method of claim 23 , wherein the trench shielding region extends substantially the length of the gate trench.