Monolithic high voltage switching devices
View Patent ↗Metal oxide semiconductor (MOS) power devices are provided including a MOS channel including a semiconductor material having high electron mobility on a silicon carbide (SiC) layer. Related methods are also provided herein.
1. A metal oxide semiconductor (MOS) power device, comprising:
a MOS channel including a semiconductor material having high electron mobility on a p-type silicon carbide (SiC) layer,
wherein the device comprises a bipolar device; and
wherein the p-type SiC layer is an anode of the SiC bipolar device; and
an n − SiC layer on the p-type SiC layer, wherein the n − SiC layer has a thickness of from about 5.0 μm to about 200 μm and a carrier concentration of from about 1.0×10 13 cm −3 to about 1.0×10 16 cm −3 .
2. The MOS power device of claim 1 , wherein the semiconductor material having high electron mobility comprises at least one of silicon, germanium, gallium arsenide and gallium nitride and wherein the SiC layer comprises at least one of a silicon carbide substrate, an implanted SiC layer and a SiC epitaxial layer.
3. The MOS power device of claim 1 , further comprising:
an n + SiC layer on the n − SiC layer, the n + SiC layer having a carrier concentration that is higher than the carrier concentration of the n − SiC layer.
4. The MOS power device of claim 3 , wherein the n + SiC layer has thickness of about 2000 Å, a carrier concentration of greater than about 1.0×10 18 cm −3 and is a cathode of the SiC bipolar device.
5. The MOS power device of claim 3 , further comprising:
p-type SiC well regions in the n− SiC layer, the p-type SiC well regions having a doping concentration of from about 1.0×10 18 cm −3 to about 5.0×10 20 cm −3 and serving as an emitter for the bipolar SiC device.
6. The MOS power device of claim 5 , wherein the p-type SiC well regions extend from about 0.1 μm to about 2.0 μm into the n − SiC layer.
7. The MOS power device of claim 6 , further comprising:
a dielectric layer on the p-type well regions;
a semiconductor layer on the dielectric layer on the p-type well regions and including the semiconductor material having high electron mobility, the semiconductor layer including n + doped portions to provide source regions and n − doped portions to provide voltage absorbing regions; and
emitter contacts on the n + doped portions,
8. The MOS power device of claim 7 , further comprising a collector contact on a surface of the p-type SiC layer opposite the n − SiC layer.
9. The MOS power device of claim 8 , wherein the device withholds a gate pinch-off voltage of about 40 V.
10. A metal oxide semiconductor (MOS) power device, comprising:
a MOS channel including a semiconductor material having high electron mobility on an n-type silicon carbide (SiC) layer, wherein the device comprises a unipolar device;
an n − SiC layer on the n-type SiC layer; and
an n + SiC layer on the n − SiC layer, the n + SiC layer having a carrier concentration that is higher than the carrier concentration of the n − SiC layer,
wherein the n − SiC layer has a thickness of from about 5.0 μm to about 200 μm and a carrier concentration of from about 5.0×10 14 cm −3 to about 1.0×10 17 cm −3 .
11. The MOS power device of claim 10 , wherein the n + SiC layer has thickness of from about 0.05 μm to about 1.0 μm and a carrier concentration of greater than about 1.0×10 18 cm −3 .
12. The MOS power device of claim 10 , further comprising:
p-type SiC well regions in the n − SiC layer, the p-type SiC well regions having a doping concentration of from about 1.0×10 18 cm −3 to about 5.0×10 20 cm −3 .
13. The MOS power device of claim 12 , wherein the p-type SiC well regions extend from about 0.1 μm to about 2.0 μm into the n − SiC layer.
14. The MOS power device of claim 12 , further comprising:
a dielectric layer on the p-type well regions;
a semiconductor layer on the dielectric layer on the p-type well regions and including the semiconductor material having high electron mobility, the semiconductor layer including n + doped portions to provide source regions and n − doped portions to provide voltage absorbing regions; and
source contacts on the n + doped portions.
15. The MOS power device of claim 14 , further comprising a drain contact on a surface of the n-type SiC layer opposite the n − SiC layer.
16. The MOS power device of claim 10 , wherein the semiconductor material having high electron mobility comprises at least one of silicon, germanium, gallium arsenide and gallium nitride and wherein the n-type SiC layer comprises at least one of a silicon carbide substrate, an implanted SiC layer and a SiC epitaxial layer.