MULTI-GATE SWITCH FIELD EFFECT TRANSISTOR
A multi-gate switch field effect transistor, FET, according to some embodiments includes a semiconductor structure, a source contact on the semiconductor structure, and a drain contact on the semiconductor structure. The multi-gate switch FET further includes a first gate on the semiconductor structure between the source contact and the drain contact; and a second gate on the semiconductor structure adjacent to the first gate and between the source contact and the drain contact. The multi-gate switch FET further includes a conducting region in the semiconductor structure between the first gate and the second gate.
1 . A multi-gate switch field effect transistor, FET, comprising:
a semiconductor structure;
a source contact on the semiconductor structure;
a drain contact on the semiconductor structure;
a first gate on the semiconductor structure between the source contact and the drain contact;
a second gate on the semiconductor structure adjacent to the first gate and between the source contact and the drain contact; and
a conducting region in the semiconductor structure between the first gate and the second gate.
2 . The multi-gate switch FET of claim 1 , wherein the conducting region comprises an N-plus material.
3 . The multi-gate switch FET of claim 1 , wherein the conducting region comprises a Group Ill nitride doped with at least one of silicon (Si) and germanium (Ge).
4 . The multi-gate switch FET of claim 1 , wherein the conducting region comprises a Group Ill nitride implanted with at least one of silicon (Si) and germanium (Ge).
5 . The multi-gate switch FET of claim 1 , wherein the conducting region comprises a regrowth N-plus layer of gallium nitride (GaN).
6 . The multi-gate switch FET of claim 1 , wherein the conducting region comprises an N-plus material and an ohmic metal on the N-plus material.
7 . The multi-gate switch FET of claim 1 , wherein the conducting region is positioned between a first portion of the semiconductor structure and a second portion of the semiconductor structure.
8 . The multi-gate switch FET of claim 7 , further comprising:
a first portion of a dielectric material on the semiconductor structure, the first portion of the dielectric material having a first length that extends from a first edge of the source contact to a first edge of the first gate;
a second portion of the dielectric material on the conducting region and on the first and second portions of the semiconductor substrate, the second portion of the dielectric material comprising (i) a second length that extends from a second edge of the first gate to a first edge of the conducting region, (ii) a third length that extends from the first edge of the conducting region to a second edge of the conducting region, and (iii) a fourth length that extends from the second edge of the conducting region to a second edge of the second gate; and
a third portion of the dielectric material on the semiconductor substrate, the third portion of the dielectric material having a fifth length that extends from a first edge of the drain contact to a first edge of the second gate.
9 . The multi-gate switch FET of claim 8 , wherein the first length and the fifth length are about the same.
10 . The multi-gate switch FET of claim 8 , wherein a distance between a second edge of the first gate and a second edge of the second gate is about equal to about the second length plus the fourth length plus the third length.
11 . The multi-gate switch FET of claim 8 , wherein the first length and the second length are about the same.
12 . The multi-gate switch FET of claim 8 , wherein the fourth length and the fifth length are about the same.
13 . The multi-gate switch FET of claim 8 , wherein the first length, the second length, the fourth length, and the fifth length are about the same.
14 . The multi-gate switch FET of claim 8 , wherein the third length is in a range from about 1 μm to about 4 μm.
15 . The multi-gate switch FET of claim 1 , wherein the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square.
16 . A multi-gate switch field effect transistor, FET, comprising:
a semiconductor structure;
a source contact on the semiconductor structure;
a drain contact on the semiconductor structure;
a first gate on the semiconductor structure between the source contact and the drain contact;
a second gate on the semiconductor structure adjacent to the first gate and between the source contact and the drain contact; and
a first conducting region in the semiconductor structure comprising a first portion positioned between the first gate and the second gate and a second portion and is connected to at least one of a ground, the source contact, and the drain contact.
17 . The multi-gate switch FET of claim 16 , wherein the second portion of the first conducting region is connected to the ground.
18 . The multi-gate switch FET of claim 16 , wherein the first gate comprises a first gate finger, the second gate comprises a second gate finger, and the second portion of the first conducting region is positioned under at least one of the first gate finger and the second gate finger.
19 . The multi-gate switch FET of claim 16 , further comprising:
a third gate on the semiconductor structure adjacent to the second gate and between the source contact and the drain contact; and
a second conducting region in the semiconductor structure comprising at least a third portion positioned between the second gate and the third gate.
20 . The multi-gate switch FET of claim 16 , wherein the first conducting region comprises an N-plus material.
21 . The multi-gate switch FET of claim 16 , wherein the first conducting region comprises a Group Ill nitride doped with at least one of silicon (Si) and germanium (Ge).
22 . The multi-gate switch FET of claim 16 , wherein the first conducting region comprises a Group Ill nitride implanted with at least one of silicon (Si) and germanium (Ge).
23 . The multi-gate switch FET of claim 16 , wherein the first conducting region comprises a regrowth N-plus layer of gallium nitride (GaN).
24 . The multi-gate switch FET of claim 16 , wherein the first conducting region comprises an N-plus material and an ohmic metal on the N-plus material.
25 . The multi-gate switch FET of claim 16 , wherein the first conducting region is positioned between a first portion of the semiconductor structure and a second portion of the semiconductor structure.
26 . The multi-gate switch FET of claim 25 , further comprising:
a first portion of a dielectric material on the semiconductor structure, the first portion of the dielectric material having a first length that extends from a first edge of the source contact to a first edge of the first gate;
a second portion of the dielectric material on the conducting region and on the first and second portions of the semiconductor substrate, the second portion of the dielectric material comprising (i) a second length that extends from a second edge of the first gate to a first edge of the conducting region, (ii) a third length that extends from the first edge of the conducting region to a second edge of the conducting region, and (iii) a fourth length that extends from the second edge of the conducting region to a second edge of the second gate; and
a third portion of the dielectric material on the semiconductor substrate, the third portion of the dielectric material having a fifth length that extends from a first edge of the drain contact to a first edge of the second gate.
27 . The multi-gate switch FET of claim 26 , wherein the first length and the fifth length are about the same.
28 . The multi-gate switch FET of claim 26 , wherein a distance between a second edge of the first gate and a second edge of the second gate is about equal to about the second length plus the fourth length plus the third length.
29 . The multi-gate switch FET of claim 26 , wherein the first length and the second length are about the same.
30 . The multi-gate switch FET of claim 26 , wherein the fourth length and the fifth length are about the same.
31 . The multi-gate switch FET of claim 26 , wherein the first length, the second length, the fourth length, and the fifth length are about the same.
32 . The multi-gate switch FET of claim 26 , wherein the third length is in a range from about 1 μm to about 4 μm.
33 . The multi-gate switch FET of claim 16 , wherein the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square.