Vertical FET structure
A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other and on the first source/emitter implant. A first elongated gate contact and a second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.
1. A vertical field effect transistor (FET) structure comprising:
a silicon carbide substrate having a top surface and a bottom surface opposite the top surface;
a drain/collector contact on the bottom surface of the silicon carbide substrate;
an epitaxial structure on the top surface of the silicon carbide substrate and having formed therein a first source/emitter implant;
a gate dielectric on a portion of the epitaxial structure;
a first plurality of source/emitter contact segments spaced apart from each other and on a continuous portion of the first source/emitter implant such that the gate dielectric is not below the first plurality of source/emitter contact segments;
a first elongated gate contact and a second elongated gate contact on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact; and
a first plurality of inter-gate plates that extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first plurality of source/emitter contact segments.
2. The vertical FET structure of claim 1 further including at least a first transistor cell and a second transistor cell such that the first elongated gate contact forms part of the first transistor cell and the second elongated gate contact forms part of the second transistor cell, wherein additional internal capacitance is provided where each of the first plurality of inter-gate plates overlaps a portion of the first source/emitter implant and the first plurality of inter-gate plates are separated by the gate dielectric.
3. The vertical FET structure of claim 2 wherein the first source/emitter implant is shared by the first transistor cell and the second transistor cell.
4. The vertical FET structure of claim 3 wherein the first transistor cell and the second transistor cell are metal oxide semiconductor field effect transistor (MOSFET) cells.
5. The vertical FET structure of claim 3 wherein the first transistor cell and the second transistor cell are insulated gate bipolar transistor (IGBT) cells.
6. The vertical FET structure of claim 1 wherein the epitaxial structure further includes a first source/emitter well in which the first source/emitter implant is provided.
7. The vertical FET structure of claim 6 wherein the silicon carbide substrate and the first source/emitter implant are doped with a material having a first polarity, and the first source/emitter well is doped with a material having a second polarity, which is opposite that of the first polarity.
8. The vertical FET structure of claim 6 wherein the silicon carbide substrate and the first source/emitter well are doped with a material having a first polarity and the first source/emitter implant is doped with a material having a second polarity, which is opposite that of the first polarity.
9. The vertical FET structure of claim 1 wherein each of the first plurality of inter-gate plates extends completely between the first elongated gate contact and the second elongated gate contact through a space formed between an adjacent pair of the first plurality of source/emitter contact segments.
10. The vertical FET structure of claim 1 wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of inter-gate plates are formed from a same material.
11. The vertical FET structure of claim 1 wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of inter-gate plates are formed from a same material and on a common plane.
12. The vertical FET structure of claim 1 wherein the epitaxial structure is formed from silicon carbide.
13. The vertical FET structure of claim 1 wherein a portion of the first elongated gate contact overlaps a first portion of the first source/emitter implant, and a portion of the second elongated gate contact overlaps a second portion of the first source/emitter implant.
14. The vertical FET structure of claim 1 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is greater than 170.
15. The vertical FET structure of claim 1 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is greater than 250.
16. The vertical FET structure of claim 1 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is greater than 350.
17. The vertical FET structure of claim 1 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is between 200 and 750.
18. The vertical FET structure of claim 1 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is between 300 and 1,000.
19. The vertical FET structure of claim 1 wherein the epitaxial structure further includes a second source/emitter implant that is spaced apart from the first source/emitter implant and further comprising:
a second plurality of source/emitter contact segments spaced apart from each other and on the second source/emitter implant, such that the gate dielectric is not below the second plurality of source/emitter contact segments;
a third elongated gate contact on the gate dielectric and positioned such that the second source/emitter implant is below and between the first elongated gate contact and the third elongated gate contact; and
a second plurality of inter-gate plates that extend from at least one of the first elongated gate contact and the third elongated gate contact into spaces formed between the second plurality of source/emitter contact segments, wherein additional internal capacitance is provided where each of the second plurality of inter-gate plates overlaps a portion of the second source/emitter implant and the first plurality of inter-gate plates are separated by the gate dielectric.
20. The vertical FET structure of claim 19 wherein:
each of the first plurality of inter-gate plates extends completely between the first elongated gate contact and the second elongated gate contact through a space formed between an adjacent pair of the first plurality of source/emitter contact segments; and
each of the second plurality of inter-gate plates extends completely between the first elongated gate contact and the third elongated gate contact through a space formed between an adjacent pair of the second plurality of source/emitter contact segments.
21. The vertical FET structure of claim 19 wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of inter-gate plates are formed from a same material.
22. The vertical FET structure of claim 19 wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of inter-gate plates are formed from a same material and on a common plane.
23. The vertical FET structure of claim 22 wherein the epitaxial structure is formed from silicon carbide.
24. The vertical FET structure of claim 19 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is between 200 and 750.
25. The vertical FET structure of claim 19 further comprising a gate-source/emitter capacitance and a gate-drain/collector capacitance, wherein a ratio of the gate-source/emitter capacitance to the gate-drain/collector capacitance is greater than 350.
26. A metal oxide semiconductor field effect transistor (MOSFET) structure comprising:
a silicon carbide substrate having a top surface and a bottom surface opposite the top surface;
a drain contact on the bottom surface;
a silicon carbide epitaxial structure on the top surface of the silicon carbide substrate and having formed therein a source/emitter implant;
a source contact having a plurality of source contact segments spaced apart from each other on the source/emitter implant and a gate contact on the silicon carbide epitaxial structure, wherein a ratio of a gate-source capacitance, as measured between the gate contact and the source contact, to a gate-drain capacitance, as measured between the gate contact and the drain contact, is greater than 250.
27. The MOSFET structure of claim 26 wherein the ratio of the gate-source capacitance to the gate-drain capacitance is greater than 350.
28. The MOSFET structure of claim 26 wherein the ratio of the gate-source capacitance to the gate-drain capacitance is between 250 and 750.
29. The MOSFET structure of claim 26 wherein the ratio of the gate-source capacitance to the gate-drain capacitance is between 300 and 1,000.