METAL STACK WITH PHONON SCATTERING LAYER THAT FORMS A NON-OHMIC CONTACT TO A SEMICONDUCTOR LAYER
A transistor device includes a semiconductor body and a non-ohmic contact on the semiconductor body. The non-ohmic contact includes a phonon scattering layer on the semiconductor body, a protection layer on a surface of the phonon scattering layer opposite the semiconductor body, and a contact layer on a surface of the protection layer opposite the phonon scattering layer. The phonon scattering layer has a work function in a range of about 4.5 eV to about 5.7 eV and a melting point in a range of about 1550° C. to about 3200° C.
1 . A transistor device comprising:
a semiconductor body; and
a non-ohmic contact on the semiconductor body, wherein the non-ohmic contact comprises:
a phonon scattering layer on the semiconductor body, the phonon scattering layer having a work function in a range of about 4.5 eV to about 5.7 eV and a melting point in a range of about 1550° C. to about 3200° C.;
a protection layer on a surface of the phonon scattering layer opposite the semiconductor body; and
a contact layer on a surface of the protection layer opposite the phonon scattering layer.
2 . The transistor device of claim 1 , wherein the phonon scattering layer comprises ruthenium (Ru).
3 . The transistor device of claim 1 , wherein the phonon scattering layer comprises at least one of rhenium (Re), rhodium (Rh), niobium (Nb), palladium (Pd), osmium (Os), or iridium (Ir).
4 . The transistor device of claim 1 , wherein a thickness of the phonon scattering layer is in a range of about 5 nm to about 35 nm.
5 . The transistor device of claim 1 , wherein a thickness of the protection layer is in a range of about 5 nm to about 40 nm.
6 . The transistor device of claim 1 , wherein a thickness of the contact layer is greater than about 100 nm.
7 . The transistor device of claim 1 , wherein a ratio of a first thickness of the phonon scattering layer to a second thickness of the protection layer is about 1:1.
8 . The transistor device of claim 1 , wherein a ratio of a first thickness of the phonon scattering layer to a second thickness of the protection layer is about to 1:2.
9 . The transistor device of claim 1 , wherein a ratio of a first thickness of the phonon scattering layer to a second thickness of the protection layer is about 1:3.
10 . The transistor device of claim 2 , wherein a thickness of the phonon scattering layer is in a range of about 5 nm to about 35 nm, a thickness of the protection layer is in a range of about 5 nm to about 40 nm, and a thickness of the contact layer is greater than about 100 nm.
11 . The transistor device of claim 1 , wherein the semiconductor body comprises one or more Group III nitride epitaxial layers.
12 . The transistor device of claim 11 , wherein the one or more Group III nitride epitaxial layers comprises at least one of a gallium nitride layer and an aluminum gallium nitride layer.
13 . The transistor device of claim 11 , further comprising:
a silicon carbide substrate, wherein the semiconductor body is on a surface of the silicon carbide substrate.
14 . The transistor device of claim 1 , wherein the transistor device comprises a gallium nitride (GaN) based high-electron mobility transistor (HEMT).
15 . The transistor device of claim 1 , wherein the protection layer comprises titanium (Ti) and the contact layer comprises gold (Au).
16 . The transistor device of claim 1 , wherein the non-ohmic contact forms a Schottky junction with the semiconductor body.
17 . A transistor device comprising:
a semiconductor body;
a gate electrode, a source electrode, and a drain electrode on the semiconductor body; and
a metal stack between the semiconductor body and at least a portion of the gate electrode, wherein the metal stack comprises:
a layer of ruthenium (Ru) on the semiconductor body;
a protection layer on a surface of the layer of ruthenium (Ru) opposite the semiconductor body;
a diffusion barrier layer on the surface of the protection layer opposite the layer of ruthenium (Ru); and
a contact layer on the surface of the diffusion barrier layer opposite the protection layer.
18 . The transistor device of claim 17 , wherein a thickness of the layer of ruthenium (Ru) is in a range of about 5 nm to 35 nm.
19 . The transistor device of claim 17 , wherein a thickness of the protection layer is in a range of about 5 nm to about 20 nm.
20 . The transistor device of claim 17 , wherein a thickness of the diffusion barrier layer is in a range of about 5 nm to about 20 nm
21 . The transistor device of claim 17 , wherein a thickness of the contact layer is greater than about 100 nm.
22 . The transistor device of claim 17 , wherein the protection layer comprises a first protection layer and a second protection layer, and a thickness of the layer of ruthenium (Ru) is about 5 nm, a thickness of the first protection layer is about 15 nm, a thickness of the second protection layer is about 10 nm, a thickness of the diffusion barrier layer is about 20 nm, and a thickness of the contact layer is greater than 100 nm.
23 . The transistor device of claim 22 , wherein the first protection layer comprises a material having a stress that is opposite a stress of the layer of ruthenium.
24 . The transistor device of claim 22 , wherein the first protection layer comprises titanium (Ti).
25 . The transistor device of claim 22 , wherein the second protective layer obstructs diffusion of atoms from the contact layer.
26 . The transistor device of claim 17 , wherein the semiconductor body comprises one or more Group III nitride epitaxial layers.
27 . The transistor device of claim 26 , wherein the one or more Group III nitride epitaxial layers comprises at least one of a gallium nitride layer and an aluminum gallium nitride layer.
28 . The transistor device of claim 17 , further comprising:
a silicon carbide substrate, wherein the semiconductor body is on a surface of the silicon carbide substrate.
29 . The transistor device of claim 17 , wherein the transistor device comprises a gallium-nitride (GaN) based high-electron mobility transistor HEMT.
30 . The transistor device of claim 17 , wherein the protection layer comprises titanium (Ti), the diffusion barrier layer comprises platinum (Pt) and the contact layer comprises gold (Au).