Devices including ultra-short gates and methods of forming same
View Patent ↗Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.
1. A device comprising:
a semiconductor including a gate recess that includes a bottom surface and a sidewall including a dielectric spacer that is formed on a sidewall of a preliminary recess, the gate recess including a recess width that is greater than about 0.05 μm;
a carbon based polymer deposited on a side wall of the dielectric spacer; and
a gate formed in the gate recess and having the recess width.
2. The device according to claim 1 , wherein the preliminary recess comprises a width that is greater than about 0.3 μm.
3. The device according to claim 1 , wherein the preliminary recess is formed using a dry etch process on a photolithography pattern on the semiconductor.
4. The device according to claim 1 , wherein the recess width is in a range of about 0.10 μm to about 0.20 μm.
5. The device according to claim 1 , further comprising a passivation layer on the semiconductor, wherein the gate recess is formed in the passivation layer and exposes the semiconductor therethrough.
6. The device according to claim 1 , wherein the dielectric spacer includes a top surface that is lower than a height of a sidewall of the preliminary recess.
7. The device according to claim 1 , wherein the dielectric spacer is formed from a dielectric spacer layer that comprises SiO and that is dry etched using a fluorine dry reactive ion etch and/or inductively coupled plasma.
8. The device according to claim 1 , wherein the dielectric spacer is formed from a dielectric spacer layer that comprises SiN and that is dry etched using a chlorine dry reactive ion etch and/or inductively coupled plasma.
9. The device according to claim 1 , wherein the gate comprises:
a gate metallization pattern in the gate recess.
10. The device according to claim 2 , wherein the preliminary recess comprises a width that is less than about 0.4 μm.
11. The device according to claim 1 ,
wherein the gate comprises a width that is less than about 0.25 μm.
12. The device according to claim 1 , wherein the gate includes a includes a gate oxide layer that includes a top surface that is higher than a bottom surface of the dielectric spacer relative to the semiconductor.
13. The device according to claim 1 , wherein the gate comprises a gate oxide layer on a bottom surface of the gate recess.
14. A device comprising:
a semiconductor including a gate recess that includes a bottom surface of a preliminary gate recess and a sidewall including a dielectric spacer that is formed on a sidewall of the preliminary recess, the gate recess including a recess width that is less than about 0.25 μm; and
a carbon based polymer deposited on a side wall of the dielectric spacer using a fluorine carbon gas having a carbon to fluorine ratio greater than or equal to about 1:2.
15. The device according to claim 14 , wherein the dielectric spacer includes a top surface that is lower than a height of a sidewall of the preliminary recess.
16. The device according to claim 14 , wherein the dielectric spacer is formed from a dielectric spacer layer that comprises SiO and that is dry etched using a fluorine dry reactive ion etch and/or inductively coupled plasma.
17. The device according to claim 14 , wherein the dielectric spacer is formed from a dielectric spacer layer that comprises SiN and that is dry etched using a chlorine dry reactive ion etch and/or inductively coupled plasma.
18. The device according to claim 14 , further comprising a gate that is formed in the gate recess, wherein the gate comprises:
a gate metallization pattern in the gate recess.
19. The device according to claim 14 , wherein the gate recess includes the recess width that is greater than about 0.05 μm.
20. The device according to claim 14 , wherein the carbon to fluorine ratio less than or equal to about 1:1.
21. A device comprising:
a semiconductor including a first surface;
a passivation layer that is on the first surface of the semiconductor; and
a gate recess that is formed in the passivation layer and includes a bottom surface that is the first surface of the semiconductor and a sidewall including a dielectric spacer that is formed on a sidewall of a preliminary recess, the gate recess including a recess width that is toss than about 0.25 μm;
a carbon based polymer deposited on a side wall of the dielectric spacer using a fluorine carbon gas; and
a gate that is formed in the gate recess.
22. The device according to claim 21 , wherein the gate comprises a gate oxide layer on the first surface of the semiconductor.
23. The device according to claim 21 , wherein the gate recess includes the recess width that is greater than about 0.05 μm.