Methods of fabricating normally-off semiconductor devices

1. A method of forming a semiconductor device, comprising:

providing a Group III-nitride buffer layer;

providing a Group III-nitride barrier layer on the Group III-nitride buffer layer;

providing a non-conducting spacer layer on the Group III-nitride barrier layer;

etching the Group III-nitride barrier layer and the spacer layer to form a trench, the trench extending through the barrier layer and exposing a portion of the buffer layer;

providing a gate structure on the spacer layer and in the trench; and

providing a gate electrode on the gate structure.

2. The method of claim 1 , wherein the forming the gate structure comprises forming a dielectric layer and wherein the dielectric layer has a thickness of from about 60 Å to about 600 Å.

3. The method of claim 1 , wherein etching further comprises etching a portion of the Group III-nitride buffer layer and wherein forming the gate structure comprises forming an aluminum nitride (AlN) layer on the spacer layer and in the trench and forming a dielectric layer on the AlN layer.

4. The method of claim 3 , wherein forming the gate structure further comprises forming a gallium nitride (GaN) layer on the AlN layer, the GaN layer being between the dielectric layer and the AlN layer.

5. The method of claim 1 , further comprising forming a silicon nitride layer on the non-conducting spacer layer such that the silicon nitride layer is part of the spacer layer.

6. The method of claim 5 , wherein the silicon nitride layer comprises a high purity silicon nitride layer.

7. A method of fabricating a semiconductor device, comprising:

providing a Group III-nitride barrier layer;

providing a non-conducting spacer layer on the Group III-nitride barrier layer;

etching the spacer layer to form a trench, the trench extending through the spacer layer and exposing at least a portion of the Group III-nitride barrier layer;

providing a gate implant region in a portion of the barrier layer;

providing a gate electrode in the trench on the gate implant region and on the spacer layer, wherein providing the gate implant region comprises:

implanting dopant ions into the exposed portion of the barrier layer with an implant energy of from about from about 3.0 keV to about 20 keV and a dose of from about 5.0×10 12 cm −2 to about 1.0×10 14 cm −2 ; and

annealing the implanted dopant ions for from about 30 seconds to about 10 minutes at a temperature of from about 1000° C. to about 1300° C.

8. The method of claim 7 , wherein annealing the implanted dopant ions comprises annealing the implanted dopant ions in an ammonia containing atmosphere.

9. The method of claim 8 , wherein the dopant ions comprise magnesium (Mg) or zinc (Zn).

10. The method of claim 8 , wherein annealing the implanted dopant ions is followed by performing an activation anneal of the implanted dopant ions for about 1.0 minute to about 1.0 hour the implant at a temperature of from about 600° C. to about 900° C.

11. The method of claim 10 , wherein the activation anneal is performed in an atmosphere containing about 80 percent N 2 and 20 percent 0 2 .

12. A method of forming a semiconductor device, comprising:

providing a Group III-nitride buffer layer;

providing a Group III-nitride barrier layer on the Group III-nitride buffer layer;

providing a non-conducting spacer layer on the Group III-nitride barrier layer;

providing a high purity silicon nitride layer on the non-conducting spacer layer such that the high purity silicon nitride layer is part of the non-conducting spacer layer;

etching the Group III-nitride barrier layer and the spacer layer to form a trench, the trench extending through the barrier layer and exposing a portion of the buffer layer;

providing a gate structure on the spacer layer and in the trench; and

providing a gate electrode on the gate structure.

13. A method of forming transistor, comprising:

providing a Group III-nitride barrier layer;

providing a non-conducting spacer layer on the Group III-nitride barrier layer, the spacer layer defining a trench extending through the spacer layer and exposing a portion of the barrier layer;

providing dielectric sidewall spacers that extend only on sidewalls of the non-conducting spacer layer in the trench;

providing a gate implant region in a portion of the barrier layer; and

providing a gate electrode in the trench on the implanted region and on the spacer layer.

14. The method of claim 13 , wherein providing the gate implant region comprises providing a gate implant region having an implant dose of from about 5.0×10 12 cm −2 to about 1.0×10 14 cm −2 .

15. The method of claim 13 , wherein providing the dielectric sidewall spacers comprises providing the dielectric sidewall spacers having a thickness of from about 10 mm to about 50.0 nm.

16. The method of claim 13 , further comprising:

providing a second non-conducting spacer layer on the gate electrode and the spacer layer; and

providing a field plate on the second non-conducting spacer.

17. The method of claim 16 , wherein the field plate is electrically coupled to a source electrode or the gate electrode.

18. The method of claim 16 , wherein the second non-conducting spacer has a thickness of from about 500 Å to about 5000 Å.

19. The method of claim 13 , wherein the trench extends into the barrier layer.

20. The method of claim 19 , wherein the trench extends from about 0 Å to about 200 Å into the barrier layer.

21. The method of claim 13 , wherein forming the transistor comprises forming a normally-off High Electron Mobility Transistor (HEMT).