Limiting failures caused by dendrite growth on semiconductor chips
A semiconductor chip comprises a substrate, a die attach material, and a die. The substrate comprises an upper surface and a lower surface opposing the upper surface. The die attach material is on the upper surface of the substrate. The die comprises a bottom surface bonded to the upper surface of the substrate by the die attach material, a top surface opposing the bottom surface, and a side wall adjacent to the top surface and the bottom surface. A shortest distance across an exterior of the side wall from the bottom surface to the top surface defines an exterior surface distance. The die further comprises a die height measured from where the side wall meets the bottom surface to where the side wall meets the top surface. The exterior surface distance is longer than the die height.
1. A semiconductor chip comprising:
a substrate comprising an upper surface and a lower surface opposing the upper surface;
a die attach material on the upper surface of the substrate; and
a die comprising:
a bottom surface bonded to the upper surface of the substrate by the die attach material;
a top surface opposing the bottom surface;
a side wall adjacent to the top surface and the bottom surface, wherein a shortest distance across an exterior of the side wall from the bottom surface to the top surface defines an exterior surface distance; and
a die height measured from where the side wall meets the bottom surface to where the side wall meets the top surface, the exterior surface distance being longer than the die height;
wherein the side wall comprises a first vertical surface, a second vertical surface, and an intermediate surface that is adjacent to each of the first vertical surface and the second vertical surface;
wherein the first vertical surface and second vertical surface are laterally offset from each other; and
wherein the intermediate surface is non-perpendicular to each of the first vertical surface and the second vertical surface.
2. The semiconductor chip of claim 1 , wherein the intermediate surface forms interior angles with the first and second vertical surfaces and one of the interior angles is between thirty-five degrees and fifty-five degrees.
3. The semiconductor chip of claim 1 , wherein the intermediate surface is spaced over the die attach material.
4. The semiconductor chip of claim 1 , wherein the intermediate surface forms an acute exterior angle with the first vertical surface and an acute interior angle with the second vertical surface.
5. The semiconductor chip of claim 1 , wherein:
the intermediate surface comprises a first intermediate surface and a second intermediate surface;
the first intermediate surface and the first vertical surface meet to form an exterior obtuse angle; and
the second intermediate surface and the second vertical surface meet to form an acute interior angle.
6. The semiconductor chip of claim 1 , wherein:
the first vertical surface is adjacent to the top surface;
the second vertical surface is adjacent to the bottom surface;
the intermediate surface is curved such that a concave cavity in the side wall is formed;
the intermediate surface increasingly straightens as the intermediate surface approaches the first vertical surface; and
the intermediate surface forms an acute interior angle with the second vertical surface.
7. The semiconductor chip of claim 1 , wherein:
the first vertical surface is adjacent to the top surface;
the second vertical surface is adjacent to the bottom surface;
the first vertical surface is curved such that a concave cavity in the side wall is formed;
the intermediate surface is curved in a direction opposite that of the first vertical surface such that a protrusion is formed; and
the intermediate surface increasingly straightens as the intermediate surface approaches the second vertical surface.
8. The semiconductor chip of claim 1 , wherein the die attach material is silver sintered.
9. The semiconductor chip of claim 1 , wherein the exterior surface distance is longer than the die height by at least 5 microns.
10. The semiconductor chip of claim 1 , wherein the semiconductor chip is air cavity packaged.
11. The semiconductor chip of claim 1 , further comprising a gallium nitride-based high-electron-mobility transistor.
12. The semiconductor chip of claim 1 , further comprising a gallium nitride-based monolithic microwave integrated circuit.
13. The semiconductor chip of claim 1 , further comprising a gallium nitride-based transistor grown on silicon carbide.
14. The semiconductor chip of claim 1 , further comprising a silicon carbide-based metal-oxide-semiconductor field-effect transistor.
15. The semiconductor chip of claim 1 , wherein the first vertical surface and the second vertical surface are each adjacent to either the top surface or the bottom surface of the die.
16. A semiconductor chip comprising:
a substrate comprising an upper surface and a lower surface opposing the upper surface;
a die attach material on the upper surface of the substrate; and
a die comprising:
a bottom surface bonded to the upper surface of the substrate by the die attach material;
a top surface that opposes, and is narrower than, the bottom surface; and
a side wall adjacent to the top surface and the bottom surface, wherein the side wall comprises:
a recess that is at least 5 microns deep and that extends around a perimeter of the die; and
a first vertical surface, a second vertical surface, and an intermediate surface that is adjacent to each of the first vertical surface and the second vertical surface;
wherein the first vertical surface and second vertical surface are laterally offset from each other; and
wherein the intermediate surface is non-perpendicular to each of the first vertical surface and the second vertical surface.
17. The semiconductor chip of claim 16 , wherein the intermediate surface forms interior angles with the first and second vertical surfaces and one of the interior angles is between thirty-five degrees and fifty-five degrees.
18. The semiconductor chip of claim 16 , wherein the intermediate surface is spaced over the die attach material.
19. The semiconductor chip of claim 16 , wherein the intermediate surface forms an acute exterior angle with the first vertical surface and an acute interior angle with the second vertical surface.
20. The semiconductor chip of claim 16 , wherein:
the intermediate surface comprises a first intermediate surface and a second intermediate surface;
the first intermediate surface and the first vertical surface meet to form an exterior obtuse angle; and
the second intermediate surface and the second vertical surface meet to form an acute interior angle.
21. The semiconductor chip of claim 16 , wherein:
the first vertical surface is adjacent to the top surface;
the second vertical surface is adjacent to the bottom surface;
the intermediate surface is curved such that a concave cavity in the side wall is formed;
the intermediate surface increasingly straightens as the intermediate surface approaches the first vertical surface; and
the intermediate surface forms an acute interior angle with the second vertical surface.
22. The semiconductor chip of claim 16 , wherein:
the first vertical surface is adjacent to the top surface;
the second vertical surface is adjacent to the bottom surface;
the first vertical surface is curved such that a concave cavity in the side wall is formed;
the intermediate surface is curved in a direction opposite that of the first vertical surface such that a protrusion is formed; and
the intermediate surface increasingly straightens as the intermediate surface approaches the second vertical surface.
23. The semiconductor chip of claim 16 , wherein the die attach material is silver sintered.
24. The semiconductor chip of claim 16 , wherein the semiconductor chip is air cavity packaged.
25. The semiconductor chip of claim 16 , further comprising a gallium nitride-based high-electron-mobility transistor.
26. The semiconductor chip of claim 16 , further comprising a gallium nitride-based monolithic microwave integrated circuit.
27. The semiconductor chip of claim 16 , further comprising a gallium nitride-based transistor grown on silicon carbide.
28. The semiconductor chip of claim 16 , further comprising a silicon carbide-based metal-oxide-semiconductor field-effect transistor.
29. The semiconductor chip of claim 16 , wherein the first vertical surface and the second vertical surface are each adjacent to either the top surface or the bottom surface of the die.