Power semiconductor devices including multiple gate bond pads
Power semiconductor devices comprise a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.
1 . A semiconductor device, comprising:
a silicon carbide based semiconductor layer structure comprising an active region defined therein;
a gate bond pad that is on a first side of the semiconductor layer structure and vertically overlapping the active region;
a source contact that is on the first side of the semiconductor layer structure;
a source bond pad on the first side of the semiconductor layer structure and electrically connected to the source contact; and
a gate bus connector electrically connected to the gate bond pad, the gate bus connector between the source contact and the source bond pad and vertically overlapping the source contact and the source bond pad.
2 . The semiconductor device of claim 1 , wherein more than half the gate bond pad vertically overlaps the active region.
3 . The semiconductor device of claim 1 , further comprising:
a plurality of source regions in the active region, wherein
the source contact is electrically connected to the plurality of source regions, and the source contact extends underneath the gate bond pad.
4 . The semiconductor device of claim 3 , further comprising:
a gate bus that is electrically connected to the gate bond pad; and
a dielectric layer that covers the gate bus and the source contact.
5 . The semiconductor device of claim 4 , wherein the source bond pad is electrically connected to the source contact through one or more first conductive vias that extend through the dielectric layer.
6 . The semiconductor device of claim 4 , further comprising a conductive gate connector that is underneath the gate bond pad and is electrically connected to the gate bond pad through a second conductive via that extends through the dielectric layer.
7 . The semiconductor device of claim 1 , wherein the gate bond pad comprises a first gate bond pad, and the semiconductor device further comprises a second gate bond pad that is spaced apart from the first gate bond pad, and
wherein the second gate bond pad is on the semiconductor layer structure and vertically overlaps the active region.
8 . The semiconductor device of claim 7 , further comprising a third gate bond pad that is positioned between the first gate bond pad and the second gate bond pad.
9 . The semiconductor device of claim 7 , further comprising a third gate bond pad and a fourth gate bond pad, wherein the first, second, third and fourth gate bond pads are positioned above respective first, second, third and fourth corner regions of the semiconductor layer structure.
10 . The semiconductor device of claim 1 , further comprising:
a plurality of source regions in the active region that are electrically connected to the source contact; and
a gate bus that is electrically connected to the gate bond pad,
wherein the gate bus is electrically connected to the gate bus connector.
11 . The semiconductor device of claim 1 , wherein the gate bond pad comprises a first gate bond pad, and
the semiconductor device further comprises:
a second gate bond pad that is on the semiconductor layer structure, vertically overlaps the active region and is spaced apart from the first gate bond pad in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure;
a first gate resistor that is electrically connected to the first gate bond pad and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction; and
a second gate resistor that is electrically connected to the second gate bond pad and extends longitudinally in the second horizontal direction.
12 . The semiconductor device of claim 1 , wherein the gate bus connector is between the source contact and the source bond pad.
13 . The semiconductor device of claim 1 , wherein the gate bus connector is between the source contact and the gate bond pad.
14 . The semiconductor device of claim 1 , wherein the gate bond pad and the gate bus connector are electrically connected through a gate electrode, the gate electrode extending under the source bond pad.
15 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor.
16 . The semiconductor device of claim 1 , further comprising a conductive gate bus plug that is electrically connected to the gate bus connector and a field oxide layer, the field oxide layer in between the conductive gate bus plug and the semiconductor layer structure and underneath and vertically overlapping the source bond pad, wherein a first of gate electrode in a plurality of gate electrodes is between the field oxide layer and the conductive gate bus plug.
17 . A semiconductor device, comprising:
a silicon carbide based semiconductor layer structure comprising an active region defined therein, the semiconductor layer structure comprising a silicon carbide drift region having a first conductivity type, a plurality of silicon carbide well regions having a second conductivity type that is different than the first conductivity type on the silicon carbide drift region, and a plurality of silicon carbide source regions having the first conductivity type in the respective silicon carbide well regions;
a source contact that is electrically connected to the plurality of silicon carbide source regions;
a plurality of gate electrodes on a first side of the semiconductor layer structure;
a first gate pad on the first side of the semiconductor layer structure; and
a second gate pad on the first side of the semiconductor layer structure,
wherein the first gate pad is above and vertically overlapping the source contact.
18 . The semiconductor device of claim 17 , further comprising a gate bus connector and a dielectric layer that is interposed between the source contact and the gate bus connector.
19 . The semiconductor device of claim 18 , further comprising a conductive gate bus plug that is in the dielectric layer, protrudes from the gate bus connector toward the semiconductor layer structure and contacts one of the plurality of gate electrodes.
20 . The semiconductor device of claim 17 , further comprising a first gate bus connector and a second gate bus connector, and
the first gate bus connector extends longitudinally in a first horizontal direction that is parallel to an upper surface of the semiconductor layer structure, and the second gate bus connector protrudes from the first gate bus connector and extends longitudinally in a second horizontal direction that is parallel to the upper surface of the semiconductor layer structure and is different from the first horizontal direction.
21 . The semiconductor device of claim 17 , wherein the first gate pad vertically overlaps the active region.
22 . The semiconductor device of claim 17 , further comprising:
a conductive gate connector, wherein a gate bond pad vertically overlaps the conductive gate connector; and
a conductive via that is interposed between the gate bond pad and the conductive gate connector and contacts both the gate bond pad and the conductive gate connector.
23 . The semiconductor device of claim 17 , further comprising a gate bus connector, a gate bus and a conductive gate bus plug,
wherein the plurality of gate electrodes comprises a first gate electrode, and
wherein the conductive gate bus plug is electrically connected to the gate bus connector and the first gate electrode, and an upper surface of the gate bus connector is higher than an upper surface of the conductive gate bus plug.
24 . The semiconductor device of claim 23 , wherein the conductive gate bus plug contacts the first gate electrode.
25 . The semiconductor device of claim 17 , wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor.
26 . A semiconductor device, comprising:
a silicon carbide based semiconductor layer structure comprising an active region defined therein;
a plurality of source regions in the active region;
a source bond pad on a first side of the semiconductor layer structure;
a gate bond pad on the first side of the semiconductor layer structure;
a plurality of gate electrodes on the semiconductor layer structure;
a conductive gate bus plug that is electrically connected to the gate bond pad; and
a field oxide layer in between the conductive gate bus plug and the semiconductor layer structure and underneath and vertically overlapping the source bond pad.
27 . A semiconductor device, comprising:
a silicon carbide based semiconductor layer structure comprising a drift region comprising an active region defined therein;
a plurality of source regions in the active region;
a source contact that is electrically connected to the plurality of source regions;
a plurality of gate electrodes on a first side of the semiconductor layer structure;
a first gate pad on the first side of the semiconductor layer structure;
a second gate pad on the first side of the semiconductor layer structure;
a gate bus that is electrically connected to the plurality of gate electrodes; and
a source bond pad on the first side of the semiconductor layer structure that is electrically connected to the source contact; and
a gate bus connector that is electrically connected to the gate bus, the gate bus connector between the source contact and the source bond pad and vertically overlapping the source contact and the source bond pad.