Wafer-level die attach metallization
View Patent ↗Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.
1. A semiconductor wafer comprising:
a semiconductor structure;
a front-side metallization on a front-side of the semiconductor structure, the front-side metallization comprising a plurality of front-side metallization elements for a plurality of semiconductor die areas of the semiconductor wafer;
a plurality of vias that extend from a back-side of the semiconductor structure to the plurality of front-side metallization elements of the front-side metallization on the front-side of the semiconductor structure;
a back-side metallization on the back-side of the semiconductor structure and within the plurality of vias such that, for each via of the plurality of vias, a portion of the back-side metallization is within the via and around a periphery of the via;
for each via of the plurality of vias, one or more barrier layers on the portion of the back-side metallization that is within the via and around the periphery of the via; and
a wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the plurality of vias and around the peripheries of the plurality of vias.
2. The semiconductor wafer of claim 1 further comprising streets through the wafer-level die attach metallization that correspond to cut-lines at which the semiconductor wafer is to be cut to separate the plurality of semiconductor die areas to thereby provide a corresponding plurality of semiconductor dies.
3. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one or more diffusion barrier layers that prevent diffusion of the wafer-level die attach metallization into the portion of the back-side metallization that is within the via and around the periphery of the via.
4. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one or more barrier layers having a surface tension sufficient to repel the wafer-level die attach metallization away from the via when melted during attachment of a corresponding semiconductor die to a package.
5. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one or more dielectric layers.
6. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one or more metal layers.
7. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one or more dielectric layers and one or more metal layers.
8. The semiconductor wafer of claim 1 wherein, for each via of the plurality of vias, the one or more barrier layers comprise one of a group consisting of: one or more inorganic composites and one or more organic composites.
9. The semiconductor wafer of claim 1 wherein the wafer-level die attach metallization is a eutectic metal alloy.
10. The semiconductor wafer of claim 9 wherein the eutectic metal alloy is Gold-Tin (AuSn) in a mixture of approximately 80% Au and approximately 20% Sn.
11. The semiconductor wafer of claim 1 wherein the back-side metallization is both electrically and thermally connected to the plurality of front-side metallization elements of the front-side metallization through the plurality of vias.
12. A semiconductor die comprising:
a semiconductor structure;
a front-side metallization element on a front-side of the semiconductor structure;
a via that extends from a back-side of the semiconductor structure to the front-side metallization element;
a back-side metallization on the back-side of the semiconductor structure and within the via such that a portion of the back-side metallization is within the via and around a periphery of the via;
one or more barrier layers on the portion of the back-side metallization that is within the via and around the periphery of the via; and
a wafer-level die attach metallization on the back-side metallization laterally adjacent to the via.
13. The semiconductor die of claim 12 wherein the wafer-level die attach metallization thermally and electrically connects the semiconductor die to a package.
14. The semiconductor die of claim 13 wherein the wafer-level die attach metallization is directly on a package contact of the package.
15. The semiconductor die of claim 12 wherein the one or more barrier layers comprise one or more diffusion barrier layers that prevent diffusion of the wafer-level die attach metallization into the portion of the back-side metallization that is within the via and around the periphery of the via.
16. The semiconductor die of claim 12 wherein the one or more barrier layers comprise one or more diffusion barrier layers having a surface tension sufficient to repel the wafer-level die attach metallization away from the via when melted during soldering of the semiconductor die to a package.
17. The semiconductor die of claim 12 wherein the wafer-level die attach metallization is a eutectic metal alloy.
18. The semiconductor die of claim 17 wherein the eutectic metal alloy is Gold-Tin (AuSn) in a mixture of approximately 80% Au and approximately 20% Sn.
19. The semiconductor die of claim 12 wherein the back-side metallization is both electrically and thermally connected to the front-side metallization element through the via.
20. A semiconductor wafer comprising:
a semiconductor structure;
a front-side metallization on a front-side of the semiconductor structure;
a back-side metallization on a back-side of the semiconductor structure;
a wafer-level die attach metallization on the back-side metallization; and
streets through the wafer-level die attach metallization that correspond to cut-lines at which the semiconductor wafer is to be cut to separate the semiconductor wafer into a plurality of semiconductor dies.
21. The semiconductor wafer of claim 20 wherein, after dicing the semiconductor wafer, each die of the plurality of semiconductor dies is electrically and thermally attached to a package via the wafer-level die attach metallization.