Robust transistors with fluorine treatment
View Patent ↗A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
1. A high electron mobility transistor (HEMT), comprising:
a buffer layer;
a barrier layer on said buffer layer;
a gate on said barrier layer;
a two dimensional electron gas (2 DEG) at the interface between said buffer layer and said barrier layer; and
a negative ion region in said barrier layer below and extending beyond an edge of said gate.
2. The HEMT of claim 1 , further comprising source and drain contacts on said barrier layer.
3. The HEMT of claim 1 , wherein said buffer and barrier layers are made of Group-III nitride materials, and said negative ion region comprises fluorine ions.
4. The HEMT of claim 1 , wherein said negative ion region is positioned to counter and reduce the HEMTs operating electric (E) field.
5. The HEMT of claim 2 , wherein said gate is between said source and drain contacts, said negative ion region being at least partially below said gate.
6. The HEMT of claim 1 , wherein said negative ion region has different depths in said barrier layer.
7. The HEMT of claim 1 , wherein said negative ion region comprises different concentrations of negative ions at different locations.
8. The HEMT of claim 1 , wherein said negative ion region is introduced into said barrier layer by plasma treatment.
9. The HEMT of claim 1 , further comprising a field plate.
10. The HEMT of claim 1 , wherein said negative ion region extends into said buffer layer.
11. A semiconductor based device, comprising:
a plurality of active semiconductor layers experiencing an operating electric (E) field;
a gate on said semiconductor layers; and
a negative ion region within at least one of said plurality of semiconductor layers and arranged at least partially beyond a region below said gate to counter said operating (E) field.
12. The semiconductor device of claim 11 , comprising a high electron mobility transistor (HEMT).
13. The semiconductor device of claim 11 , wherein said active semiconductor layers comprise Group-III nitride materials and wherein said negative ion region comprises fluorine ions.
14. The semiconductor device of claim 11 , wherein said negative ion region has sections with different depths in said active semiconductor layers.
15. The semiconductor device of claim 11 , wherein said negative ion region comprises different concentrations of negative ions at different locations.
16. A high electron mobility transistor (HEMT), comprising:
a Group-III nitride based buffer layer;
a Group-III nitride based barrier layer on said buffer layer;
a two dimensional electron gas (2 DEG) at the heterointerface between said buffer layer and said barrier layer;
a source and drain contacts on said barrier layer;
a gate on said barrier between said source and drain contacts; and
a fluorine negative ion region arranged below said barrier layer and extending beyond an edge of said gate toward said drain to counter operating electric (E) field in said HEMT.
17. The HEMT of claim 16 , wherein said negative ion region is at least partially in said barrier layer.
18. The HEMT of claim 16 , wherein said negative ion region is at least partially in said buffer layer.
19. The HEMT of claim 16 , wherein said negative ion region is at least partially under said gate.
20. The HEMT of claim 16 , further comprising a field plate.