POWER SILICON CARBIDE BASED SEMICONDUCTOR DEVICES WITH SELECTIVE JFET IMPLANTS THAT ARE SELF-ALIGNED WITH THE WELL REGIONS AND METHODS OF MAKING SUCH DEVICES
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift layer having a first conductivity type, a JFET region that has the first conductivity type in the upper portion of the drift layer, a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region when viewed in plan view, and a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions. The JFET region comprises a plurality of spaced-apart first JFET sub-regions that each has a first doping concentration and a second JFET sub-region that has a second doping concentration that is lower than the first doping concentration, the second JFET region extending around at least one of the first JFET sub-regions when viewed in plan view.
1 . A semiconductor device, comprising:
a semiconductor layer structure that includes a drift layer having a first conductivity type;
a JFET region that has the first conductivity type in the upper portion of the drift layer;
a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region when viewed in plan view; and
a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions,
wherein the JFET region comprises a plurality of spaced-apart first JFET sub-regions that each has a first doping concentration and a second JFET sub-region that has a second doping concentration that is lower than the first doping concentration, the second JFET region extending around at least one of the first JFET sub-regions when viewed in plan view.
2 . The semiconductor device of claim 1 , wherein the first JFET sub-regions comprise implanted regions and the second JFET sub-region comprises an un-implanted region.
3 . The semiconductor device of claim 1 , wherein the plurality of well regions are arranged in columns, where the well regions in adjacent columns are offset from each other in a column direction.
4 . The semiconductor device of claim 3 , wherein each well region has a hexagonal shape when viewed in plan view.
5 . The semiconductor device of claim 4 , wherein each first JFET sub-region has an annular hexagonal shape when viewed in plan view.
6 . The semiconductor device of claim 4 , wherein each first JFET sub-region surrounds a respective one of the well regions when viewed in plan view.
7 . The semiconductor device of claim 4 , wherein each first JFET sub-region is positioned between a respective one of the well regions and the second JFET sub-region when the semiconductor device is viewed in plan view.
8 . The semiconductor device of claim 1 , wherein the second JFET sub-region comprises a continuous region that surrounds each of the first JFET sub-regions.
9 . The semiconductor device of claim 1 , wherein the plurality of well regions are arranged in columns, where the well regions in adjacent columns are offset from each other in a column direction.
10 . A semiconductor device, comprising:
a semiconductor layer structure that includes a drift layer having a first conductivity type;
a JFET region that has the first conductivity type in the upper portion of the drift layer;
a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region; and
a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions,
wherein the FET region comprises a plurality of spaced-apart first JFET sub-regions that each has a first doping concentration and a second JFET sub-region that has a second doping concentration that is lower than the first doping concentration, the second JFET region extending around at least one of the well regions.
11 . The semiconductor device of claim 10 , wherein the first JFET sub-regions comprise implanted regions and the second JFET sub-region comprises an un-implanted region.
12 . The semiconductor device of claim 10 , wherein the plurality of well regions are arranged in columns.
13 . The semiconductor device of claim 12 , wherein the well regions in adjacent columns are offset from each other in a column direction.
14 . The semiconductor device of claim 13 , wherein each first JFET sub-region has an annular hexagonal shape when viewed in plan view.
15 . The semiconductor device of claim 14 , wherein each first JFET sub-region surrounds a respective one of the well regions when viewed in plan view.
16 . The semiconductor device of claim 12 , wherein each first JFET sub-region has an annular rectangular shape when viewed in plan view.
17 . The semiconductor device of claim 10 , wherein the second JFET sub-region comprises a continuous region that surrounds each of the first JFET sub-regions.
18 . A semiconductor device, comprising:
a semiconductor layer structure that includes a drift layer having a first conductivity type;
a JFET region that has the first conductivity type in the upper portion of the drift layer;
a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region; and
a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions,
wherein the FET region comprises a continuous first JFET sub-region that extends around the plurality of well regions and that has a first doping concentration and a plurality of spaced-apart second JFET sub-regions that each has a second doping concentration, where the second doping concentration is lower than the first doping concentration.
19 . The semiconductor device of claim 18 , wherein the first JFET sub-region comprises an implanted region and the second JFET sub-regions comprise un-implanted regions.
20 . The semiconductor device of claim 18 , wherein each well region has a hexagonal shape when viewed in plan view.
21 . The semiconductor device of claim 20 , wherein each second FET sub-region has a triangular shape when viewed in plan view.
22 - 56 . (canceled)