Patent Application

App. No. 18/443,031

Abstract

Claims (46)

1 . A semiconductor die, comprising:

a semiconductor structure; and

a multilayer metallization structure on the semiconductor structure, the multilayer metallization structure comprising a first metallization layer and a second metallization layer on the first metallization layer, the second metallization layer having a different grain microstructure than the first metallization layer,

wherein the first metallization layer and the second metallization layer include at least one common chemical element.

2 - 3 . (canceled)

4 . The semiconductor die of claim 1 , wherein the at least one common chemical element is aluminum.

5 . The semiconductor die of claim 1 , wherein the first metallization layer comprises aluminum and the second metallization layer comprises an aluminum alloy, and wherein the aluminum alloy is one of an aluminum-copper alloy, an aluminum-magnesium alloy, or an aluminum-beryllium alloy.

6 - 8 . (canceled)

9 . The semiconductor die of claim 1 , wherein the first metallization layer comprises a first aluminum alloy, and the second metallization layer comprises a second aluminum alloy that is different from the first aluminum alloy.

10 - 14 . (canceled)

15 . The semiconductor die of claim 1 , wherein the multilayer metallization structure is a multilayer metallization stack comprising a plurality of first metallization layers and a plurality of second metallization layers, and wherein each first metallization layer and each second metallization layer is alternately arranged in a stacked arrangement.

16 - 17 . (canceled)

18 . The semiconductor die of claim 1 , wherein the multilayer metallization structure has a combined thickness greater than about 1 micron.

19 - 33 . (canceled)

34 . A semiconductor die, comprising:

a semiconductor structure; and

a multilayer metallization structure on the semiconductor structure, the multilayer metallization structure comprising a first metallization layer and a second metallization layer on the first metallization layer;

wherein a smallest grain size of the first metallization layer is greater than about 100 nanometers and a largest grain size of the second metallization layer is less than about 100 nanometers.

35 - 37 . (canceled)

38 . The semiconductor die of claim 34 , wherein the multilayer metallization structure comprises at least two first metallization layers alternately arranged between at least two second metallization layers.

39 - 41 . (canceled)

42 . The semiconductor die of claim 34 , wherein the first metallization layer comprises aluminum, and the second metallization layer comprises a copper alloy, the copper alloy being one of a copper-beryllium alloy or a copper-magnesium alloy.

43 - 44 . (canceled)

45 . The semiconductor die of claim 34 , wherein a difference between the smallest grain size of the first metallization layer and the largest grain size of the second metallization layer is about 100 nanometers.

46 . The semiconductor die of claim 34 , wherein the smallest grain size of the first metallization layer is in a range of about 100 nanometers to about 500 nanometers, and wherein the largest grain size of the second metallization layer is in a range of about 20 nanometers to about 100 nanometers.

47 - 54 . (canceled)

55 . The semiconductor die of claim 34 , wherein a thickness of the first metallization layer is substantially equal to a thickness of the second metallization layer.

56 . The semiconductor die of claim 34 , wherein a thickness of the first metallization layer is different than a thickness of the second metallization layer.

57 - 62 . (canceled)

63 . A semiconductor device package, comprising:

a submount; and

a semiconductor die on the submount, the semiconductor die comprising a multilayer metallization structure, the multilayer metallization structure comprising a first metallization layer having a thickness in a range of about 100 nanometers to about 2 microns and a second metallization layer on the first metallization layer, the second metallization layer having a thickness in a range of about 100 nanometers to about 2 microns,

wherein the first metallization layer comprises aluminum and the second metallization layer comprises an aluminum alloy.

64 - 68 . (canceled)

69 . The semiconductor device package of claim 63 , wherein the aluminum alloy is a ternary aluminum alloy comprising a ternary element, and the ternary element is one of silicon or cobalt.

70 - 76 . (canceled)

77 . The semiconductor device package of claim 63 , further comprising an encapsulating portion directly contacting the multilayer metallization structure, wherein the encapsulating portion comprises an epoxy mold compound (EMC).

78 - 79 . (canceled)

80 . The semiconductor device package of claim 63 , further comprising a passivation layer on the multilayer metallization structure, wherein the passivation layer comprises one of silicon nitride or a polymer.

81 - 83 . (canceled)

84 . The semiconductor device package of claim 63 , wherein the semiconductor device package is one of a discrete semiconductor device package or a power module.

85 . (canceled)

86 . The semiconductor device package of claim 63 , wherein the multilayer metallization structure is one or more of an electrode, an interconnect, or a bonding pad for the semiconductor die.

87 . (canceled)

88 . The semiconductor device package of claim 63 , wherein the semiconductor die comprises a wide bandgap semiconductor, the wide bandgap semiconductor comprising one of a silicon carbide-based metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide-based Schottky diode, or a Group-III nitride-based high electron mobility transistor (HEMT) device.

89 . (canceled)

Assignments (8)