Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods
Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/−1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
1. A semiconductor device, comprising:
a drift region having an upper portion and a lower portion, the drift region comprising silicon carbide;
wherein the drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 6° and 35° from a first plane that is normal to a top surface of the drift region,
wherein the p-n junction extends within +/−1.5° of one of the <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide material forming the drift region,
wherein first and second opposed sidewalls of a p-type pillar are slanted along a length of the sidewalls in the same direction with respect to the first plane and first and second opposed sidewalls of an n-type pillar are slanted along a length of the sidewalls of the n-type pillar in the same direction with respect to the first plane,
wherein the p-type pillar comprises an implanted p-type pillar and the n-type pillar comprises an implanted n-type pillar, and
wherein the p-n junction comprises an interface between the p-type pillar and the n-type pillar.
2. The semiconductor device of claim 1 , further comprising:
a first contact on the upper portion of the drift region; and
a second contact on the lower portion of the drift region,
wherein the implanted p-type and n-type pillars extend at least 4 microns into the drift region from an upper surface of the drift region.
3. The semiconductor device of claim 2 , wherein the drift region includes a plurality of p-type pillars and a plurality of n-type pillars that form a respective plurality of p-n junctions, wherein each p-n junction extends within +/−1.5° of one of the <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide material forming the drift region.
4. The semiconductor device of claim 1 , wherein the first sidewall of the implanted p-type pillar and the second sidewall of the implanted p-type pillar are slanted at the same angle with respect to the first plane.
5. The semiconductor device of claim 1 , wherein the first sidewall of the implanted p-type pillar is slanted at an angle of between 15.5° and 18.5° from the <0001> crystallographic axis.
6. A semiconductor device, comprising:
a drift region having an upper portion and a lower portion, the drift region comprising silicon carbide;
wherein the drift region includes:
a first pillar that is doped with first conductivity type impurities, the first pillar having a first sidewall that is slanted at an angle of between 10° and 13°, between 15.5° and 18.5°, or between 30° and 33° from the <0001> crystallographic axis; and
a second pillar that is doped with second conductivity type impurities that are opposite the first conductivity type impurities adjacent the first pillar,
wherein the first and second pillars comprise first and second bar-shaped pillars, and wherein a longitudinal axis of an upper surface of the first bar-shaped pillar extends perpendicular to the <11-20> crystallographic direction and parallel to the <10-10> crystallographic direction, and
wherein the first pillar and the second pillar form a p-n junction in the drift region.
7. The semiconductor device of claim 6 , further comprising:
a first contact on the upper portion of the drift region; and
a second contact on the lower portion of the drift region,
wherein the p-n junction is at least part of a superjunction structure in the drift region.
8. The semiconductor device of claim 6 , wherein the second pillar has a first sidewall that is slanted at an angle of between 10° and 13°, between 15.5° and 18.5°, or between 30° and 33° from the <0001> crystallographic axis.
9. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar is slanted at the same angle as a second sidewall of the first pillar.
10. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar faces and directly contacts the first sidewall of the second pillar.
11. The semiconductor device of claim 6 , further comprising a silicon carbide substrate between the drift region and the second contact, wherein the first conductivity type impurities are p-type conductivity impurities, and wherein the second conductivity type impurities are n-type conductivity impurities.
12. The semiconductor device of claim 11 , wherein the silicon carbide substrate is cut at an oblique angle to the plane defined by the <10-10> and <11-20> crystallographic axes.
13. The semiconductor device of claim 12 , wherein the oblique angle is between 2° and 8°.
14. The semiconductor device of claim 6 , wherein the first and second pillars extend at least 4 microns into the drift region from an upper surface of the drift region.
15. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar, a second sidewall of the first pillar and a first sidewall of the second pillar each extend at a same angle from a plane that is normal to a top surface of the drift region, wherein the angle is between 6° and 35°.
16. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar, a second sidewall of the first pillar and a first sidewall of the second pillar each extend at a same angle from a plane that is normal to a top surface of the drift region, wherein the angle is between 10° and 30°.
17. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar is slanted at an angle of between 15.5° and 18.5° from the <0001> crystallographic axis and the drift region comprises 4H silicon carbide.
18. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar is slanted at an angle of between 10° and 13° from the <0001> crystallographic axis and the drift region comprises 6H silicon carbide.
19. The semiconductor device of claim 6 , wherein the first sidewall of the first pillar is slanted at an angle of between 30° and 33° from the <0001> crystallographic axis and the drift region comprises 2H silicon carbide.
20. A semiconductor device, comprising:
a drift region having an upper portion and a lower portion, the drift region comprising silicon carbide;
wherein the drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 6° and 35° from a first plane that is normal to a top surface of the drift region,
wherein the p-n junction extends within +/−1.5° of one of the <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide material forming the drift region,
wherein first and second opposed sidewalls of a p-type pillar are slanted along a length of the sidewalls in the same direction with respect to the first plane and first and second opposed sidewalls of an n-type pillar are slanted along a length of the sidewalls of the n-type pillar in the same direction with respect to the first plane, and
wherein at least one of the p-type pillar and the n-type pillar comprises an implanted pillar, and
wherein the p-n junction comprises an interface between the p-type pillar and the n-type pillar.
21. The semiconductor device of claim 20 , wherein the drift region includes a plurality of p-type pillars and a plurality of n-type pillars that form a respective plurality of p-n junctions, wherein each p-n junction extends within +/−1.5° of one of the <11-23>, <−1-123>, <1-213>, <−12-13>, <2-1-13> or <−2113> crystallographic axes of the silicon carbide material forming the drift region.