Transistor semiconductor die with increased active area
A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.
1. A transistor semiconductor die comprising:
a drift layer;
a first dielectric layer on the drift layer;
a first metallization layer on the first dielectric layer, wherein at least a portion of the first metallization layer provides a first contact pad;
a second dielectric layer on the first metallization layer;
a second metallization layer on the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad;
a first plurality of electrodes electrically coupled to the first metallization layer and covered by the first dielectric layer;
a second plurality of electrodes electrically coupled to the second metallization layer such that the transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad;
an edge termination region; and
a device region, wherein a total inactive area within the device region is less than an area of the second contact pad.
2. The transistor semiconductor die of claim 1 wherein the transistor semiconductor die is configured to conduct more than 0.5 A between the first contact pad and the third contact pad in a forward conduction mode of operation and block more than 100 V between the first contact pad and the third contact pad in a blocking mode of operation.
3. The transistor semiconductor die of claim 1 wherein the drift layer comprises silicon carbide.
4. The transistor semiconductor die of claim 1 further comprising a passivation layer over the second metallization layer such that the first contact pad and the second contact pad are exposed through the passivation layer.
5. The transistor semiconductor die of claim 1 wherein the transistor semiconductor die is a metal-oxide-semiconductor field-effect transistor (MOSFET).
6. The transistor semiconductor die of claim 1 wherein the transistor semiconductor die is an insulated gate bipolar transistor (IGBT).
7. The transistor semiconductor die of claim 1 wherein the transistor semiconductor die provides a vertical transistor device such that the third contact pad is opposite the drift layer from the first contact pad and the second contact pad.
8. The transistor semiconductor die of claim 1 wherein the second metallization layer is coupled to the second plurality of electrodes by one or more vias through the first dielectric layer and the second dielectric layer.
9. The transistor semiconductor die of claim 1 further comprising one or more sensor contact pads on the second dielectric layer.
10. The transistor semiconductor die of claim 9 wherein the one or more sensor contact pads are coupled to a sensor on the second dielectric layer.
11. The transistor semiconductor die of claim 10 wherein the sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.
12. The transistor semiconductor die of claim 9 wherein the one or more sensor contact pads are coupled to a sensor in the drift layer by one or more vias through the first dielectric layer and the second dielectric layer.
13. The transistor semiconductor die of claim 12 wherein the sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.
14. The transistor semiconductor die of claim 9 wherein at least a portion of the one or more sensor contact pads overlaps the first metallization layer.
15. The transistor semiconductor die of claim 9 wherein an area of the first contact pad is at least 0.4 mm 2 .
16. The transistor semiconductor die of claim 1 wherein at least a portion of the second metallization layer overlaps the first metallization layer.
17. The transistor semiconductor die of claim 1 wherein the first dielectric layer and the second dielectric layer comprise one or more of SiO 2 , al 2 O 3 , and Si 3 N 4 .
18. The transistor semiconductor die of claim 17 wherein the first dielectric layer has a different composition than the second dielectric layer.
19. The transistor semiconductor die of claim 1 further comprising an intervening layer between the first dielectric layer and the second dielectric layer such that the intervening layer is between the first metallization layer and the second dielectric layer.
20. The transistor semiconductor die of claim 19 wherein:
the first dielectric layer, the second dielectric layer, and the intervening layer comprise one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 ; and
the intervening layer has a different composition than the first dielectric layer and the second dielectric layer.
21. The transistor semiconductor die of claim 19 further comprising an additional intervening layer between the second dielectric layer and the second metallization layer.
22. The transistor semiconductor die of claim 21 wherein:
the first dielectric layer, the second dielectric layer, the intervening layer, and the additional intervening layer comprise one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 ; and
the intervening layer and the additional intervening layer have a different composition than the first dielectric layer and the second dielectric layer.
23. The transistor semiconductor die of claim 1 wherein the transistor semiconductor die is a vertical transistor device.
24. A transistor semiconductor die comprising:
a drift layer;
a first dielectric layer on the drift layer;
a first metallization layer on the first dielectric layer, wherein at least a portion of the first metallization layer provides a first contact pad;
a second dielectric layer on the first metallization layer;
a second metallization layer on the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad;
a first plurality of electrodes electrically coupled to the first metallization layer and covered by the first dielectric layer;
a second plurality of electrodes electrically coupled to the second metallization layer; and
one or more sensor contact pads on the second dielectric layer.
25. The transistor semiconductor die of claim 24 , wherein the transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.
26. The transistor semiconductor die of claim 24 wherein the one or more sensor contact pads are coupled to a sensor on the second dielectric layer.
27. The transistor semiconductor die of claim 26 wherein the sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.
28. The transistor semiconductor die of claim 24 wherein the one or more sensor contact pads are coupled to a sensor in the drift layer by one or more vias through the first dielectric layer and the second dielectric layer.
29. The transistor semiconductor die of claim 28 wherein the sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.
30. The transistor semiconductor die of claim 24 wherein at least a portion of the one or more sensor contact pads overlaps the first metallization layer.
31. A transistor semiconductor die comprising:
a drift layer;
a first dielectric layer on the drift layer;
a first metallization layer on the first dielectric layer, wherein at least a portion of the first metallization layer provides a first contact pad;
a second dielectric layer on the first metallization layer;
a second metallization layer on the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad;
a first plurality of electrodes electrically coupled to the first metallization layer and covered by the first dielectric layer;
a second plurality of electrodes electrically coupled to the second metallization layer; and
an intervening layer between the first dielectric layer and the second dielectric layer such that the intervening layer is between the first metallization layer and the second dielectric layer.
32. The transistor semiconductor die of claim 31 , wherein the transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.
33. The transistor semiconductor die of claim 31 wherein:
the first dielectric layer, the second dielectric layer, and the intervening layer comprise one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 ; and
the intervening layer has a different composition than the first dielectric layer and the second dielectric layer.
34. The transistor semiconductor die of claim 31 further comprising an additional intervening layer between the second dielectric layer and the second metallization layer.
35. The transistor semiconductor die of claim 34 wherein:
the first dielectric layer, the second dielectric layer, the intervening layer, and the additional intervening layer comprise one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 ; and
the intervening layer and the additional intervening layer have a different composition than the first dielectric layer and the second dielectric layer.