IP Library Granted Patent US 11,355,630
Granted Patent B2
US 11,355,630 · App. 17/018,305 · Granted Jun 7, 2022

Trench bottom shielding methods and approaches for trenched semiconductor device structures

Inventors: Woongsun Kim (Cary, NC); Daniel J. Lichtenwalner (Raleigh, NC); Naeem Islam (Morrisville, NC); Sei-Hyung Ryu (Cary, NC)
Assignee: Wolfspeed, Inc.
H01L29/7813H01L29/41741H01L29/42376H01L29/66477
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Quick Facts
Patent No.
US 11,355,630
App. No.
17/018,305
Granted
Jun 7, 2022
Kind
B2
Abstract

Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Claims (30)

1. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type;

a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and

a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench,

wherein the first sidewall of each gate trench is free from the polysilicon layer.

2. The device of claim 1 , further comprising an oxide layer on each polysilicon layer.

3. The device of claim 1 , further comprising gate structures within respective gate trenches, wherein each gate structure comprises a gate oxide.

4. The device of claim 1 , wherein the semiconductor layer structure comprises well regions having a second conductivity type that is different from the first conductivity type.

5. The device of claim 1 , further comprising a first source/drain contact on a first major surface of the semiconductor layer structure and a second source/drain contact on a second major surface of the semiconductor layer structure opposite from the first major surface.

6. The device of claim 1 , wherein each gate trench extends in length in a direction parallel to an upper surface of the semiconductor layer structure, and wherein each polysilicon layer extends the length of the respective gate trench.

7. The device of claim 1 , wherein each gate trench extends in length in a direction parallel to an upper surface of the semiconductor layer structure, and wherein each gate trench comprises a first length portion comprising the respective polysilicon layer and a second length portion free of the respective polysilicon layer.

8. The device of claim 1 , further comprising a lower oxide layer on the bottom surface, the first sidewall, and the second sidewall of each gate trench, wherein the polysilicon layer is on the lower oxide layer.

9. The device of claim 8 , further comprising an upper oxide layer on the polysilicon layer.

10. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type;

a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and

a plurality of polysilicon layers, each polysilicon layer at a bottom of a respective gate trench of the plurality of gate trenches and in direct contact with the drift region.

11. The device of claim 10 , wherein each gate trench of the device comprises a respective polysilicon layer of the plurality of polysilicon layers.

12. The device of claim 11 , further comprising a gate structure in each gate trench.

13. The device of claim 11 , wherein each gate trench extends in length in a direction parallel to an upper surface of the semiconductor layer structure, and wherein each polysilicon layer extends the length of the respective gate trench.

14. The device of claim 11 , wherein each gate trench extends in length in a direction parallel to an upper surface of the semiconductor layer structure, and wherein each gate trench comprises a first length portion comprising the respective polysilicon layer and a second length portion free of the respective polysilicon layer.

15. A device comprising:

a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type;

a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternating along a length of the gate trench; and

a plurality of polysilicon layers, each polysilicon layer directly on the second sidewall of a respective gate trench in the first length portions,

wherein the second length portions of each gate trench are free from the polysilicon layers.

16. The device of claim 15 , further comprising an oxide layer within each gate trench.

17. The device of claim 16 , wherein the oxide layer comprises a first cross-section in the first length portions of each gate trench and a second cross-section in the second length portions of each gate trench, the first and second cross-sections differing from each other.

18. The device of claim 16 , further comprising a gate structure within respective gate trenches, wherein the gate structure comprises a gate electrode.

19. The device of claim 18 , wherein the gate electrode comprises a first cross-section in the first length portions of each gate trench and a second cross-section in the second length portions of each gate trench.

Assignments (9)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
CHANGE OF NAME Recorded Jan 21, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 058809/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2020
From: KIM, WOONGSUN; LICHTENWALNER, DANIEL J.; ISLAM, NAEEM; RYU, SEI-HYUNG
To: CREE, INC.
Reel/Frame 054600/0333 →
Cited By (1)
US 12,666,658