Semiconductor die with improved ruggedness
A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
1. A semiconductor die comprising:
a substrate, the substrate comprising boundaries defined by a substrate termination edge;
an active region that is isolated from the substrate termination edge by a barrier region; and
a charge redistribution path on the barrier region, wherein the charge redistribution path is coupled to a potential.
2. The semiconductor die of claim 1 , wherein the potential is ground.
3. The semiconductor die of claim 1 , wherein the charge redistribution path comprises a metal layer.
4. The semiconductor die of claim 3 , wherein the metal layer comprises one or more of aluminum, titanium, silicon, nickel, platinum, gold, and germanium.
5. The semiconductor die of claim 1 , wherein the charge redistribution path is inset from the substrate termination edge.
6. The semiconductor die of claim 1 , wherein the charge redistribution path forms a ring around a perimeter of the substrate.
7. The semiconductor die of claim 1 , wherein the charge redistribution path forms a first pattern along a first lateral edge of the substrate and a second pattern along a second lateral edge of the substrate, and the first pattern is different than the second pattern.
8. The semiconductor die of claim 7 , wherein a gate contact for the active region is arranged closer to the first lateral edge.
9. The semiconductor die of claim 1 , further comprising:
a first passivation layer over the substrate, the first passivation layer terminating at a first passivation termination edge; and
a second passivation layer over the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge that is closer to the substrate termination edge than the first passivation termination edge.
10. The semiconductor die of claim 9 , wherein the charge redistribution path is arranged between the first passivation termination edge and the second passivation termination edge.
11. The semiconductor die of claim 9 , wherein the charge redistribution path is arranged to traverse across one or more of the first passivation termination edge and the second passivation termination edge.
12. A semiconductor die comprising:
a substrate, the substrate comprising boundaries defined by a substrate termination edge;
an active region comprising one or more active devices;
a barrier region surrounding the active region, wherein the barrier region terminates at a barrier region termination edge that is inset from the substrate termination edge; and
a charge redistribution path that is formed between the barrier region termination edge and the substrate termination edge, wherein the charge redistribution path is coupled to a potential.
13. The semiconductor die of claim 12 , wherein the charge redistribution path is formed in a portion of the substrate between the barrier region termination edge and the substrate termination edge.
14. The semiconductor die of claim 12 , wherein the charge redistribution path is implanted with dopants.
15. The semiconductor die of claim 14 , wherein a conductivity of the charge redistribution path is higher than a conductivity of a surface of the active region.
16. The semiconductor die of claim 12 , wherein the charge redistribution path is an un-implanted region of the substrate.
17. The semiconductor die of claim 12 , wherein the potential is a fixed potential.
18. The semiconductor die of claim 17 , wherein the fixed potential is ground.
19. The semiconductor die of claim 12 , further comprising:
a first passivation layer over the substrate, the first passivation layer terminating at a first passivation termination edge; and
a second passivation layer over the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge that is closer to the substrate termination edge than the first passivation termination edge.
20. The semiconductor die of claim 19 , wherein the barrier region termination edge is arranged between the first passivation termination edge and the second passivation termination edge.
21. The semiconductor die of claim 19 , wherein the charge redistribution path is arranged to traverse across the second passivation termination edge.
22. The semiconductor die of claim 1 , wherein the potential is a fixed potential.