Methods of fabricating transistors having buried P-type layers coupled to the gate
View Patent ↗A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
1. A unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising:
a MESFET having a source, a drain and a gate, the gate being between the source and the drain; and
a p-type conductivity region beneath the gate between the source and the drain, the p-type conductivity region being electrically coupled to the gate, wherein portions of the p-type conductivity region and the gate extend past a mesa defining a periphery of the MESFET; and
wherein the p-type conductivity region and the gate are electrically coupled at the portions of the p-type conductivity region and the gate that extend past the mesa.
2. The MESFET of claim 1 , further comprising an n-type conductivity channel layer, wherein the gate is provided on the n-type conductivity channel layer, wherein the p-type conductivity region electrically coupled to the gate comprises a second gate and wherein the n-type conductivity channel layer has a thickness of from about 0.1 to about 0.5 μml.
3. The MESFET of claim 2 , wherein the MESFET comprises a switch and wherein the n-type conductivity channel layer having the thickness reduces an on-resistance of the switch.
4. The MESFET of claim 1 :
wherein an n-type conductivity channel layer and a substrate define the mesa, the mesa having sidewalls that define the periphery of the MESFET.
5. The MESFET of claim 4 , further comprising a metal contact on the portions of the p-type conductivity region and the gate that extend past the mesa such that the metal contact electrically couples the p-type conductivity region and the gate.
6. A metal semiconductor field effect transistor (MESFET) configured to function as a switch, the MESFET comprising:
a source, a drain and a gate, the gate being between the source and the drain on an n-type conductivity channel layer having a thickness of from about 0.1 to about 0.5 μm; and
a p-type conductivity region beneath the gate between the source and the drain, the p-type conductivity region comprising a second gate,
wherein portions of the p-type conductivity region and the gate extend past a mesa defining a periphery of the MESFET; and
wherein the p-type conductivity region and the gate are electrically coupled at the portions of the p-type conductivity region and the gate that extend past the mesa.
7. A method of forming a metal-semiconductor field-effect transistor (MESFET), the method comprising:
forming a MESFET having a source, a drain and a gate, the gate being between the source and the drain; and
forming a p-type conductivity region beneath the gate between the source and the drain, the p-type conductivity region being electrically coupled to the gate,
wherein portions of the p-type conductivity region and the gate extend past a mesa defining a periphery of the MESFET; and
wherein the p-type conductivity region and the gate are electrically coupled at the portions of the p-type conductivity region and the gate that extend past the mesa.
8. A method of forming a metal-semiconductor field-effect transistor (MESFET) configured to function as a switch, the method comprising:
forming a source, a drain and a gate, the gate being between the source and the drain on an n-type conductivity channel layer having a thickness of from about 0.1 to about 0.5 μm; and
forming a p-type conductivity region beneath the gate between the source and the drain, the p-type conductivity region comprising a second gate,
wherein portions of the p-type conductivity region and the gate extend past a mesa defining a periphery of the MESFET; and
wherein the p-type conductivity region and the gate are electrically coupled at the portions of the p-type conductivity region and the gate that extend past the mesa.
9. The MESFET of claim 1 , wherein the MESFET comprises a silicon carbide MESFET.
10. The MESFET of claim 1 , wherein the gate is provided on an n-type conductivity channel layer, the MESFET further comprising:
a p-type buffer layer spaced apart from and beneath the n-type conductivity channel layer, wherein the p-type conductivity region is provided in the p-type buffer layer.
11. The MESFET of claim 10 , wherein the p-type buffer layer comprises a first p-type buffer layer, the MESFET further comprising a second p-type buffer layer between the n-type conductivity channel layer and the first p-type buffer layer.
12. The MESFET of claim 6 , wherein the MESFET comprises a silicon carbide MESFET.
13. The MESFET of claim 6 , wherein the gate is provided on an n-type conductivity channel layer, the MESFET further comprising:
a p-type buffer layer spaced apart from and beneath the n-type conductivity channel layer, wherein the p-type conductivity region is provided in the p-type buffer layer.
14. The MESFET of claim 13 , wherein the p-type buffer layer comprises a first p-type buffer layer, the MESFET further comprising a second p-type buffer layer between the n-type conductivity channel layer and the first p-type buffer layer.