Semiconductor device with selectively grown field oxide layer in edge termination region
A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.
1 . A semiconductor device, comprising:
a drift region having a first conductivity type;
an active region in the drift region; and
a termination region in the drift region adjacent to the active region, the termination region comprising:
a guard ring on the drift region, the guard ring having a second conductivity type; and
a passivation layer over the guard ring and over the drift region in the termination region, the passivation layer having a first thickness over the guard ring and a second thickness over the drift region, wherein the first thickness is greater than the second thickness.
2 . The semiconductor device of claim 1 , wherein the active region comprises a diode structure.
3 . The semiconductor device of claim 1 , wherein:
the passivation layer is a field oxide layer; and the guard ring comprises polysilicon.
4 . The semiconductor device of claim 1 , further comprising:
a heterojunction barrier region in the drift region in the active region, the heterojunction barrier region having the second conductivity type; and
a first contact on the heterojunction barrier region and on the drift region in the active region.
5 . The semiconductor device of claim 4 , wherein the first contact is a Schottky contact.
6 . The semiconductor device of claim 4 , wherein:
the first conductivity type is an n-type conductivity; and the second conductivity type is a p-type conductivity.
7 . The semiconductor device of claim 4 , further comprising a metal overlayer over the first contact.
8 . The semiconductor device of claim 7 , wherein:
the passivation layer is a first passivation layer; and
the semiconductor device further comprises a second passivation layer over the termination region and a portion of the metal overlayer.
9 . The semiconductor device of claim 8 , wherein the second passivation layer is a polyimide layer.
10 . The semiconductor device of claim 1 , wherein:
the drift region comprises a silicon carbide region; and the drift region is disposed over a substrate.
11 . The semiconductor device of claim 1 , wherein the first thickness of the passivation layer is in a range of approximately one hundred (100) to five hundred (500) nanoangstoms (nA) and the second thickness of the passivation layer is less than one hundred (100) nA.
12 . An electronic device, comprising:
a drift region having a first conductivity type;
an edge termination region in the drift region;
a guard ring on the drift region of the edge termination region, the guard ring having a second conductivity type; and
a passivation layer on the guard ring and on the drift region in the edge termination region, the passivation layer having a first thickness over the guard ring and a second thickness over surface of the drift region, wherein the first thickness is greater than the second thickness.
13 . The electronic device of claim 12 , further comprising:
a heterojunction barrier region in the drift region in an active region of the electronic device, the heterojunction barrier region having the second conductivity type; and
a contact on the heterojunction barrier region.
14 . The electronic device of claim 13 , further comprising a metal overlayer over the contact.
15 . The electronic device of claim 13 , wherein: the active region has a first barrier height; and
the edge termination region has a second barrier height.
16 . The electronic device of claim 12 , wherein:
the passivation layer is a first passivation layer; and
the electronic device further comprises a second passivation layer over the edge termination region.
17 . The electronic device of claim 16 , wherein:
the first passivation layer is a field oxide layer; and the second passivation layer is a polyimide layer.
18 . The electronic device of claim 12 , wherein the first thickness of the passivation layer is in a range of approximately one hundred (100) to five hundred (500) nanoangstoms (nA) and the second thickness of the passivation layer is less than one hundred-(100) nA.
19 . A semiconductor device, comprising:
a drift region having a first conductivity type; an active region in the drift region; and
a termination region in the drift region adjacent to the active region, the termination region comprising:
a guard ring on the drift region, the guard ring having a second conductivity type; and
a passivation layer over at least the guard ring, wherein the passivation layer extends below a plane of a top surface of the drift region at the guard ring.
20 . The semiconductor device of claim 19 , wherein: the passivation layer is a field oxide layer; and the guard ring comprises a doped polysilicon.
21 . A termination region for a semiconductor device having a drift region of a first conductivity type, the termination region comprising:
a guard ring on the drift region, the guard ring having a second conductivity type opposite the first conductivity type; and
a passivation layer over the guard ring and over the drift region in the termination region, the passivation layer having a first thickness over the guard ring and a second thickness over the drift region, wherein the first thickness is greater than the second thickness.
22 . The termination region of claim 21 , wherein:
the semiconductor device comprises a heterojunction barrier region in the drift region in an active region of the semiconductor device, the heterojunction barrier region having the second conductivity type; the active region has a first barrier height; and
the termination region has a second barrier height.
23 . The termination region of claim 21 , wherein:
the passivation layer is a first passivation layer; and
the termination region further comprises a second passivation layer over the first passivation layer.
24 . The termination region of claim 23 , wherein:
the first passivation layer is a field oxide layer; and the second passivation layer is a polyimide layer.
25 . The termination region of claim 21 , wherein the first thickness of the passivation layer is in a range of approximately one hundred (100) to five hundred (500) nanoangstoms (nA) and the second thickness of the passivation layer is less than one hundred (100) nA.