Package for power electronics
A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.
1. A package for power electronics comprising:
a power substrate comprising a plurality of traces;
the plurality of traces comprising at least a Kelvin conductive trace on the power substrate, a control conductive trace on the power substrate, and a power switching conductive trace on the power substrate; and
at least two power semiconductor die on the power switching conductive trace,
wherein at least one of the plurality of traces comprises at least one edge that is angled with respect to edges of the power substrate.
2. The package of claim 1 , wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the power substrate.
3. The package of claim 1 , wherein at least one the plurality of traces comprises at least one edge that is V-shaped or U-shaped.
4. The package of claim 1 , wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the at least two power semiconductor die.
5. The package of claim 1 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein the first power switching contact and the second power switching contact are both arranged to extend from a same side of the package past the Kelvin conductive trace and the control conductive trace toward the at least two power semiconductor die.
6. The package of claim 5 , further comprising:
a Kelvin connection contact coupled to the Kelvin conductive trace; and
a control contact coupled to the control conductive trace,
wherein the Kelvin connection contact extends from a same side of the package as the first power switching contact and the second power switching contact; and
wherein the control contact extends from a same side of the package as the first power switching contact and the second power switching contact.
7. The package of claim 1 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein a width of the first power switching contact is structured to increase from a side of the package toward the at least two power semiconductor die.
8. The package of claim 7 , wherein the first power switching contact comprises a structure configured as a balancing connection to reduce voltage differences across the at least two power semiconductor die.
9. The package of claim 1 , wherein the control conductive trace is arranged on the power substrate between the power switching conductive trace and the Kelvin conductive trace.
10. A package for power electronics comprising:
a power substrate comprising a plurality of traces;
the plurality of traces comprising at least a Kelvin conductive trace on the power substrate, a control conductive trace on the power substrate, and a power switching conductive trace on the power substrate; and
at least two power semiconductor die on the power switching conductive trace,
wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the power substrate.
11. The package of claim 10 , wherein at least one of the plurality of traces comprises at least one edge that is angled with respect to edges of the power substrate.
12. The package of claim 10 , wherein at least one the plurality of traces comprises at least one edge that is V-shaped or U-shaped.
13. The package of claim 10 , wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the at least two power semiconductor die.
14. The package of claim 10 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein the first power switching contact and the second power switching contact are both arranged to extend from a same side of the package past the Kelvin conductive trace and the control conductive trace toward the at least two power semiconductor die.
15. The package of claim 14 , further comprising:
a Kelvin connection contact coupled to the Kelvin conductive trace; and
a control contact coupled to the control conductive trace,
wherein the Kelvin connection contact extends from a same side of the package as the first power switching contact and the second power switching contact; and
wherein the control contact extends from a same side of the package as the first power switching contact and the second power switching contact.
16. The package of claim 10 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein a width of the first power switching contact is structured to increase from a side of the package toward the at least two power semiconductor die.
17. The package of claim 16 , wherein the first power switching contact comprises a structure configured as a balancing connection to reduce voltage differences across the at least two power semiconductor die.
18. The package of claim 10 , wherein the control conductive trace is arranged on the power substrate between the power switching conductive trace and the Kelvin conductive trace.
19. A package for power electronics comprising:
a power substrate comprising a plurality of traces;
the plurality of traces comprising at least a Kelvin conductive trace on the power substrate, a control conductive trace on the power substrate, and a power switching conductive trace on the power substrate; and
at least two power semiconductor die on the power switching conductive trace,
wherein at least one the plurality of traces comprises at least one edge that is V-shaped or U-shaped.
20. The package of claim 19 , wherein at least one of the plurality of traces comprises at least one edge that is angled with respect to edges of the power substrate.
21. The package of claim 19 , wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the power substrate.
22. The package of claim 19 , wherein at least one the plurality of traces comprises at least one edge that is not parallel to any edge of the at least two power semiconductor die.
23. The package of claim 19 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein the first power switching contact and the second power switching contact are both arranged to extend from a same side of the package past the Kelvin conductive trace and the control conductive trace toward the at least two power semiconductor die.
24. The package of claim 23 , further comprising:
a Kelvin connection contact coupled to the Kelvin conductive trace; and
a control contact coupled to the control conductive trace,
wherein the Kelvin connection contact extends from a same side of the package as the first power switching contact and the second power switching contact; and
wherein the control contact extends from a same side of the package as the first power switching contact and the second power switching contact.
25. The package of claim 19 , further comprising:
a first power switching contact; and
a second power switching contact,
wherein a width of the first power switching contact is structured to increase from a side of the package toward the at least two power semiconductor die.
26. The package of claim 25 , wherein the first power switching contact comprises a structure configured as a balancing connection to reduce voltage differences across the at least two power semiconductor die.
27. The package of claim 19 , wherein the control conductive trace is arranged on the power substrate between the power switching conductive trace and the Kelvin conductive trace.