IP Library Granted Patent US 7,960,756
Granted Patent B2
US 7,960,756 · App. 12/468,537 · Granted Jun 14, 2011

Transistors including supported gate electrodes

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Quick Facts
Patent No.
US 7,960,756
App. No.
12/468,537
Granted
Jun 14, 2011
Kind
B2
Abstract

A transistor includes a protective layer having an opening extending therethrough on a substrate, and a gate electrode in the opening. First portions of the gate electrode laterally extend on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions of the gate electrode are spaced apart from the protective layer and laterally extend beyond the first portions. Related devices are also discussed.

Claims (49)

1. A transistor comprising:

source and drain contacts;

a protective layer having an opening extending therethrough, wherein the protective layer comprises a dielectric material including silicon nitride, aluminum nitride, and/or silicon dioxide; and

a gate electrode in the opening, wherein the gate electrode includes first portions laterally extending on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions spaced apart from the protective layer and laterally extending beyond the first portions, wherein the first portions of the gate electrode extend symmetrically on the surface portions of the protective layer at opposite sides of the opening.

2. A transistor comprising:

a protective layer having an opening extending therethrough;

a gate electrode in the opening, wherein the gate electrode includes first portions laterally extending on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions spaced apart from the protective layer and laterally extending beyond the first portions, wherein the first portions of the gate electrode extend symmetrically on the surface portions of the protective layer at opposite sides of the opening;

source and drain contacts; and

a passivation layer on the protective layer and on the gate electrode.

3. The transistor of claim 2 , wherein the protective layer and the passivation layer comprise a same material.

4. A transistor, comprising:

source and drain contacts;

a protective layer having a first opening extending therethrough;

a second layer on the protective layer, the second layer having a second opening extending therethrough that is wider than the first opening; and

a gate electrode in the first and second openings, wherein the gate electrode includes first portions laterally extending on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions spaced apart from the protective layer and laterally extending beyond the first portions,

wherein the first portions of the gate electrode extend symmetrically on the surface portions of the protective layer at opposite sides of the first opening, and

wherein the second portions of the gate electrode laterally extend on portions of the second layer outside the second opening.

5. The transistor of claim 4 , wherein the first and second openings define a stair-step profile.

6. The transistor of claim 4 , wherein the second layer has a lower dielectric index than the protective layer.

7. The transistor of claim 4 , wherein the gate electrode is directly on opposing sidewalls of the opening in the protective layer.

8. A transistor comprising:

a channel layer;

a barrier layer on the channel layer;

source and drain contacts on the barrier layer;

a protective layer on the barrier layer and having an opening extending therethrough; and

a gate electrode in the opening, wherein the gate electrode includes first portions laterally extending on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions spaced apart from the protective layer and laterally extending beyond the first portions,

wherein the first portions of the gate electrode extend symmetrically on the surface portions of the protective layer at opposite sides of the opening, wherein the gate electrode extends through the opening in the protective layer to contact the barrier layer, and wherein the channel layer and the barrier layer are configured to provide a High Electron Mobility Transistor (HEMT).

9. The transistor of claim 8 , further comprising:

first and second ohmic contact regions on the barrier layer at opposite sides of the gate electrode and spaced apart from the protective layer.

10. The transistor of claim 9 , wherein the protective layer has a thickness of at least about a thickness of the first and second ohmic contact regions.

11. A transistor, comprising:

a protective layer having a first opening therein;

a passivation layer on the protective layer, the passivation layer having a second opening therein that is wider than the first opening, wherein a width of the second opening is self-aligned and symmetric around a width of the first opening;

a gate electrode extending into the first and second openings, wherein the gate electrode includes first portions that laterally extend on surface portions of the protective layer outside the first opening on opposite sides thereof, and second portions that laterally extend beyond the first portions on portions of the passivation layer outside the second opening on opposite sides thereof; and

source and drain contacts.

12. The transistor of claim 11 , wherein the first portions of the gate electrode extend symmetrically on the surface portions of the protective layer at opposite sides of the first opening.

13. The transistor of claim 11 , wherein the passivation layer has a lower dielectric index than the protective layer.

14. The transistor of claim 11 , further comprising:

a channel layer; and

a barrier layer on the channel layer, wherein the protective layer is on the barrier layer,

wherein the source and drain contacts comprise first and second ohmic contact regions on the barrier layer at opposite sides of the gate electrode and spaced apart from the protective layer.

15. The transistor of claim 14 , wherein the protective layer has a thickness of at least about a thickness of the first and second ohmic contact regions.

16. The transistor of claim 11 , wherein the protective layer and the passivation layer comprise a same material.

17. A transistor, comprising:

source and drain contacts;

a protective layer having a first opening therein;

a passivation layer on the protective layer, the passivation layer having a second opening therein that is wider than the first opening, wherein a width of the second opening is self-aligned and symmetric around a width of the first opening; and

a gate electrode extending into the first and second openings, wherein the gate electrode includes first portions that laterally extend on surface portions of the protective layer outside the first opening on opposite sides thereof, and second portions that laterally extend beyond the first portions on portions of the passivation layer outside the second opening on opposite sides thereof,

wherein the gate electrode is directly on opposing sidewalls of the protective layer that define the first opening, and is directly on opposing sidewalls of the passivation layer that define the second opening.

Assignments (6)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →