Granted Patent B2

US 7,528,040 · App. 11/136,057 · Granted May 5, 2009

Abstract

Claims (56)

1. A method of forming a silicon carbide power device, comprising:

forming an n − silicon carbide layer on a silicon carbide substrate;

forming a p-type silicon carbide well region on the n − silicon carbide layer;

forming a buried region of p + silicon carbide in the p-type silicon carbide well region;

forming an n + region of silicon carbide on the buried region of p + silicon carbide, a channel region of the power device being adjacent the buried region of p + and n + region of silicon carbide;

forming an n − region on the channel region; and

removing a portion of the n − region from the channel region so that a portion of the n − region remains on the channel region to provide a reduction in a surface roughness of the channel region.

2. The method of claim 1 , wherein removing comprises performing a chemical mechanical polishing (CMP) process that removes a portion of the n − if region from the channel region.

3. The method of claim 2 , wherein the CMP process removes all but from about 1000 to about 5000 Å of the n − f region from the channel region.

4. The method of claim 2 , wherein removing further comprises removing a portion of the n − if region that is from about 2.0 to about 3.0 times a depth of the surface roughness of the channel region.

5. The method of claim 4 , wherein about 1500 Å of the n − region remains on the channel region after the CMP process.

6. The method of claim 1 , wherein the reduction in the surface roughness is a reduction in a root mean square (RMS) surface roughness of from at least about 28 Å to less than about 1.0 Å.

7. The method of claim 6 , wherein removing is followed by:

forming a sacrificial oxide layer on the remaining portion of the n-region on the channel region, the sacrificial layer having a thickness of from about 100 to about 1000 Å; and

removing the sacrificial oxide layer, wherein the RMS surface roughness is further reduced by the formation and removal of the sacrificial oxide layer from less than about 1.0 Å to about 0.70 Å.

8. The method of claim 1 , wherein forming the n 31 region comprises growing an n − epitaxial layer on the channel region to a predetermined thickness such that a portion of the n − epitaxial layer remains on the channel region after removal of the portion of the n − epitaxial layer.

9. The method of claim 8 , wherein the predetermined thickness of the n − epitaxial layer is from about 1500 Å to about 6000 Å.

10. The method of claim 2 , wherein performing the CMP process is followed by selectively etching the n − region such that the n − region is removed from the n 30 region.

11. The method of claim 1 :

wherein forming the p-type silicon carbide well region comprises implanting p-type dopants in the n − if silicon carbide layer;

wherein forming the buried region of p + silicon carbide comprises implanting p-type dopants in the p-type silicon carbide well region; and

wherein forming the n + region of silicon carbide comprises implanting n-type dopants in the p-type silicon carbide well region on the buried region of p 30 silicon carbide.

12. The method of claim 11 , further comprising activating the implanted dopants by exposing the implanted dopants to a temperature of greater than about 1600° C.

13. The method of claim 2 :

wherein forming the p-type silicon carbide well region comprises forming a p-type epitaxial layer on the n − silicon carbide layer;

wherein forming the buried region of p + silicon carbide comprises implanting p-type silicon carbide dopants in the p-type silicon carbide well region; and

wherein forming the n 30 region of silicon carbide comprises implanting n-type silicon carbide dopants in the p-type silicon carbide well region on the first and second p + regions of silicon carbide.

14. The method of claim 13 , further comprising forming an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n-type region of silicon carbide is a Junction Field Effect Transistor (JFET) region of the silicon carbide power device.

15. The method of claim 1 , further comprising forming an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n − region only remains on the channel region.

16. The method of claim 1 , wherein the substrate comprises n − substrate which serves as a drift region of the silicon carbide power device, the method further comprising forming an n + drain region on the substrate opposite the n − silicon carbide layer.

17. The method of claim 16 , wherein forming the n + drain region comprises at least one of implanting the n + drain region in the n − substrate or growing the n + drain region on the n − substrate.

18. The method of claim 1 , wherein the silicon carbide power device comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

19. A method of forming a silicon carbide power device, comprising:

growing a silicon carbide epitaxial region on a channel region of the power device;

mechanically removing a portion of the silicon carbide epitaxial region such that a remaining portion of the silicon carbide epitaxial region on the channel region provides a reduction in a surface roughness of the channel region; and then

selectively etching the silicon carbide epitaxial region to expose an underlying region while a portion of the silicon carbide epitaxial region remains on the channel region of the power device.

20. The method of claim 19 , wherein the reduction in the surface roughness is a reduction in a root mean square (RMS) surface roughness of from at least about 28 Å to less than about 1.0 Å.

21. The method of claim 20 , further comprising:

forming a sacrificial oxide layer on the remaining portion of the silicon carbide epitaxial region, the sacrificial oxide layer having a thickness of from about 100 to about 1000 Å; and

removing the sacrificial oxide layer to provide a further reduction in the surface roughness of the channel region.

22. The method of claim 21 , wherein the RMS surface roughness is further reduced by the formation and removal of the sacrificial oxide layer from less than about 1.0 Å to about 0.70 Å.

23. The method of claim 19 , wherein mechanically removing comprises performing a chemical mechanical polishing (CMP) process that removes a portion of the silicon carbide epitaxial region from the channel region.

24. The method of claim 23 , wherein a remaining portion of the silicon carbide epitaxial region after the CMP process has a thickness of from about 1000 to about 5000 Å.

25. The method of claim 19 , wherein mechanically removing further comprises mechanically removing a portion of the silicon carbide epitaxial region that is from about 2 to about 3 times a depth of the surface roughness of the channel region.

26. The method of claim 25 , wherein a remaining portion of the silicon carbide epitaxial region has a thickness of from about 1500 Å.

27. The method of claim 19 , wherein the silicon carbide epitaxial region has a thickness from about 1500 Åto about 6000 Å.

28. The method of claim 19 , further comprising:

forming an n − silicon carbide layer on a silicon carbide substrate;

forming a p-type silicon carbide well region on the n − silicon carbide layer;

forming first and second spaced apart buried regions of p + silicon carbide in the p-type silicon carbide well region; and

forming first and second spaced apart n + regions of silicon carbide on the first and second p + regions of silicon carbide, respectively, such that the channel region of the power device is defined between the first p + and n + regions of silicon carbide and the second p + and n + regions of silicon carbide.

29. The method of claim 28 :

wherein forming the p-type silicon carbide well region comprises implanting p-type dopants in the n − silicon carbide layer;

wherein forming the first and second spaced apart buried regions of p + silicon carbide comprises implanting p-type dopants in the p-type silicon carbide well region; and

wherein forming the first and second spaced apart n + regions of silicon carbide comprises implanting n-type dopants in the p-type silicon carbide well region on the first and second p + regions of silicon carbide.

30. The method of claim 29 , further comprising activating the implanted dopants by exposing the implanted dopants to a temperature of greater than about 1600 ° C.

Assignments (9)