GaN based HEMTs with buried field plates
View Patent ↗A transistor with source and drain electrodes formed in contact with an active region and a gate between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the active region surface between the gate and drain electrodes and between the gate and source electrodes. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer that is on at least part of the first active layer surface and between the gate and drain and between the gate and source. At least one conductive path electrically connects the field plate to the source electrode or the gate.
1. A transistor device, comprising:
a semiconductor structure comprising an active region, said active region comprising a barrier layer;
a source electrode in electrical contact with said semiconductor structure;
a drain electrode in electrical contact with said semiconductor structure; and
a gate between said source and drain electrodes, said gate comprising a vertical portion and a horizontal portion, said vertical portion in a recessed area of said barrier layer, said horizontal portion on said semiconductor structure and extending toward said drain on one side and toward said source on another side, wherein at least a portion of a space between said gate horizontal portion and said semiconductor structure is filled with air.
2. The transistor device of claim 1 , further comprising a first spacer layer between at least a portion of said gate and said semiconductor structure.
3. The transistor device of claim 2 , further comprising a field plate electrically connected to said source electrode.
4. The transistor device of claim 3 , wherein said field plate is electrically connected to said source electrode through at least one conductive bus.
5. The transistor device of claim 3 , wherein said field plate is electrically connected to said source electrode through a conductive path that runs outside of the area defined by the footprint of the semiconductor structure.
6. The transistor device of claim 3 , wherein said field plate is electrically connected to said source electrode through at least one conductive via.
7. The transistor device of claim 3 , wherein said field plate is on said spacer layer.
8. The transistor device of claim 1 , further comprising a substrate, said semiconductor structure on said substrate.
9. The transistor device of claim 1 , wherein said gate is T-shaped.
10. The transistor device of claim 1 , wherein said semiconductor structure comprises a buffer layer and a barrier layer.
11. The transistor of claim 1 , wherein more than one surface of said vertical portion of said gate is in direct contact with the same layer of said active region.
12. A transistor device, comprising:
a semiconductor structure comprising an active region, said active region comprising a plurality of layers;
a source electrode in electrical contact with said semiconductor structure;
a drain electrode in electrical contact with said semiconductor structure; and
a gate between said source and drain electrodes, said gate comprising a vertical portion and a horizontal portion, said vertical portion in a recessed area of said semiconductor structure active region, wherein said gate is in direct contact with said active region, said horizontal portion on said semiconductor structure and extending toward said drain on one side and toward said source on another side, wherein at least a portion of a space between said gate horizontal portion and said semiconductor structure is filled with air.