Vertical power transistor with built-in gate buffer
View Patent ↗A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.
1. A semiconductor die comprising:
a substrate;
a drift layer on the substrate;
a vertical power transistor comprising:
a pair of junction implants in the drift layer and separated by a JFET region;
a gate oxide layer and a source contact on the drift layer;
a gate contact on the gate oxide layer; and
a drain contact on the substrate opposite the drift layer; and
gate buffer circuitry configured to selectively deliver a biasing signal to the gate contact of the vertical power transistor for switching the vertical power transistor between an ON state and an OFF state, the gate buffer circuitry comprising:
a gate buffer well in the drift layer and adjacent to the vertical power transistor;
a body region on at least a portion of the gate buffer well;
a first gate buffer transistor within the body region; and
a second gate buffer transistor within the gate buffer well.
2. The semiconductor die of claim 1 wherein the vertical power transistor is a metal-oxide semiconductor field effect transistor (MOSFET).
3. The semiconductor die of claim 1 wherein the vertical power transistor is a silicon-carbide (SiC) device.
4. The semiconductor die of claim 1 wherein the gate buffer circuitry is configured to selectively deliver the biasing signal to the gate contact of the vertical power transistor based on a received control signal.
5. The semiconductor die of claim 1 wherein the first gate buffer transistor is a PMOS transistor and the second gate buffer transistor is an NMOS transistor.
6. The semiconductor die of claim 5 wherein the PMOS transistor comprises:
the body region;
a first implant well in the body region;
a second implant well that is laterally separated from the first implant well and in the body region;
a third implant well that is adjacent to and in contact with the second implant well in the body region;
a gate oxide layer on at least a portion of the body region such that the gate oxide layer partially overlaps and runs between the first implant well and the second implant well;
a gate contact on the gate oxide layer;
a drain contact on at least a portion of the first implant well; and
a source contact on at least a portion of both the second implant well and the third implant well.
7. The semiconductor die of claim 6 wherein the NMOS transistor comprises:
a fourth implant well in the gate buffer well;
a fifth implant well that is adjacent to and in contact with the fourth implant well in the gate buffer well;
a sixth implant well that is laterally separated from the fifth implant well and in the gate buffer well;
a gate oxide layer on at least a portion of the gate buffer well such that the gate oxide layer partially overlaps and runs between the fifth implant well and the sixth implant well;
a gate contact located on the gate oxide layer;
a source contact on at least a portion of both the fourth implant well and the fifth implant well; and
a drain contact on at least a portion of the sixth implant well.
8. The semiconductor die of claim 6 wherein the body region is silicon carbide (SiC).
9. The semiconductor die of claim 7 wherein:
the source contact of the PMOS transistor is coupled to a supply voltage;
the gate contact of the PMOS transistor and the gate contact of the NMOS transistor are coupled to an input node;
the drain contact of the PMOS transistor and the drain contact of the NMOS transistor are coupled to an output node;
the source contact of the NMOS transistor is coupled to ground; and
the gate contact of the vertical power transistor is coupled to the output node.
10. The semiconductor die of claim 5 wherein the PMOS transistor comprises:
a field oxide layer between the body region and the gate buffer well;
the body region;
a first implant well in the body region;
a second implant well that is laterally separated from the first implant well and in the body region;
a gate oxide layer on at least a portion of the body region such that the gate oxide layer partially overlaps and runs between the first implant well and the second implant well;
a gate contact located on the gate oxide layer;
a drain contact on at least a portion of the first implant well; and
a source contact on at least a portion of the second implant well.
11. The semiconductor die of claim 10 wherein the NMOS transistor comprises:
a third implant well in the gate buffer well;
a fourth implant well that is adjacent to and in contact with the third implant well in the gate buffer well;
a fifth implant well that is laterally separated from the fourth implant well and in the gate buffer well;
a gate oxide layer on at least a portion of the gate buffer well such that the gate oxide layer partially overlaps and runs between the fourth implant well and the fifth implant well;
a gate contact located on the gate oxide layer;
a source contact on at least a portion of both the third implant well and the fourth implant well; and
a drain contact on at least a portion of the fifth implant.
12. The semiconductor die of claim 11 wherein the body region is silicon (Si).
13. The semiconductor die of claim 11 wherein:
the source contact of the PMOS transistor is coupled to a supply voltage;
the gate contact of the PMOS transistor and the gate contact of the NMOS transistor are coupled to an input node;
the drain contact of the PMOS transistor and the drain contact of the NMOS transistor are coupled to an output node;
the source contact of the NMOS transistor is coupled to ground; and
the gate contact of the vertical power transistor is coupled to the output node.
14. The semiconductor die of claim 1 wherein:
the first gate buffer transistor is a PMOS transistor comprising a gate contact coupled to an input node, a source contact coupled to a supply voltage, and a drain contact coupled to an output node; and
the second gate buffer transistor is an NMOS transistor comprising a gate contact coupled to the input node, a drain contact coupled to the output node, and a source contact coupled to ground.
15. The semiconductor die of claim 14 wherein the gate contact of the vertical power transistor is coupled to the output node.