Power semiconductor devices including a trenched gate and methods of forming such devices
Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.
1. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure, the semiconductor layer structure having first and second major surfaces;
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming and annealing a preliminary bottom dielectric layer;
forming a conformal gate dielectric layer in the trench directly on a center portion of the bottom dielectric layer;
forming the gate electrode in the trench on the gate dielectric layer,
forming a shield region in the drift layer underneath the trench.
2. The method of claim 1 , wherein forming the preliminary bottom dielectric layer comprises forming a spin-on-glass layer, and annealing the preliminary bottom dielectric layer is performed after forming the spin-on-glass layer.
3. The method of claim 1 , wherein forming the bottom dielectric layer further comprises etching an upper portion of the preliminary bottom dielectric layer until an upper surface of the semiconductor layer structure is exposed.
4. The method of claim 1 , wherein forming the bottom dielectric layer further comprises planarizing the preliminary bottom dielectric layer.
5. The method of claim 1 , wherein the preliminary bottom dielectric layer reflows during annealing.
6. The method of claim 5 , further comprising:
forming a source contact on the first major surface of the semiconductor layer structure; and
forming a drain contact on the second major surface of the semiconductor layer structure.
7. The method of claim 6 , wherein the gate dielectric layer comprises a material that is different from the bottom dielectric layer.
8. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure;
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming a preliminary bottom dielectric layer and oxidizing the preliminary bottom dielectric layer in an environment including a network modifier, and the network modifier comprises boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb);
forming a gate electrode in the trench on the bottom dielectric layer.
9. The method of claim 8 , wherein the bottom dielectric layer comprises the network modifier.
10. The method of claim 8 , further comprising:
forming a source contact on a first major surface of the semiconductor layer structure; and
forming a drain contact on a second major surface of the semiconductor layer structure,
wherein the gate electrode is configured to control current flow through a channel that is interposed between the source contact and the drain contact.
11. The method of claim 8 , wherein the gate dielectric layer comprises a material that is different from the bottom dielectric layer.
12. The method of claim 8 , wherein forming the bottom dielectric layer further comprises annealing the preliminary bottom dielectric layer, and wherein the preliminary bottom dielectric layer reflows during annealing.
13. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure;
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming and annealing a preliminary bottom dielectric layer, wherein the preliminary bottom dielectric layer reflows during annealing; and
forming a gate electrode in the trench on the bottom dielectric layer; and
forming a barrier layer on the bottom dielectric layer before forming the gate electrode, and the barrier layer comprises a first material different from the bottom dielectric layer,
wherein the gate electrode contacts an upper surface of the barrier layer, and
wherein a center portion of the barrier layer is curved.
14. The method of claim 13 , further comprising:
forming a source contact on a first major surface of the semiconductor layer structure; and
forming a drain contact on a second major surface of the semiconductor layer structure,
wherein the gate electrode is configured to control current flow through a channel that is interposed between the source contact and the drain contact.
15. The method of claim 13 , further comprising forming a gate dielectric layer on the bottom dielectric layer, the gate dielectric layer comprising a material that is different from the bottom dielectric layer.
16. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure, wherein the semiconductor layer structure comprises a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer and a source region having the first conductivity type in an upper portion of the well;
forming a shield region in the drift layer underneath the trench by implanting an impurity element into a portion of the in the drift layer,
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming and annealing a preliminary bottom dielectric layer;
forming a gate dielectric layer in the trench so that the gate dielectric layer covers the bottom dielectric layer and directly contacts sidewalls of the trench; and
forming a gate electrode in the trench on the bottom dielectric layer,
wherein the bottom dielectric layer has a first thickness on a bottom of the trench and a second thickness on a sidewall of the trench, the second thickness being less than the first thickness.
17. The method of claim 16 , wherein the preliminary bottom dielectric layer is formed and annealed concurrently.
18. The method of claim 16 , wherein forming the preliminary bottom dielectric layer comprises depositing the preliminary bottom dielectric layer, the method further comprising planarizing the preliminary bottom dielectric layer after depositing the preliminary bottom dielectric layer and before annealing the preliminary bottom dielectric layer.
19. The method of claim 16 , further comprising:
forming a source contact on a first major surface of the semiconductor layer structure; and
forming a drain contact on a second major surface of the semiconductor layer structure,
wherein the gate electrode is configured to control current flow through a channel that is interposed between the source contact and the drain contact.
20. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure;
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming and annealing a preliminary bottom dielectric layer, and wherein the preliminary bottom dielectric layer is annealed at a temperature of at least about a glass transition temperature of the preliminary bottom dielectric layer;
forming a gate electrode in the trench on the bottom dielectric layer;
forming a source trench that is in the semiconductor layer structure and is spaced apart from the trench;
forming a shield region in the drift layer underneath the source trench; and
forming a source contact in the source trench.
21. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure;
forming a bottom dielectric layer in the trench, the bottom dielectric layer comprising boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb);
forming a gate dielectric layer on the bottom dielectric layer, the gate dielectric layer contacting an upper portion of a sidewall of the trench and comprising a first material different from the bottom dielectric layer; and then
forming a gate electrode in the trench on the bottom dielectric layer.
22. The method of claim 21 , further comprising forming a barrier layer on the bottom dielectric layer before forming the gate dielectric layer, and the barrier layer comprises a second material different from the bottom dielectric layer.
23. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure that includes a drift layer below the trench;
forming a spin-on-glass layer in the trench and then performing an oxidation process to form a bottom dielectric layer in the trench;
forming a gate dielectric layer on the bottom dielectric layer, the gate dielectric layer comprising a first material different from the bottom dielectric layer;
forming a gate electrode in the trench on the bottom dielectric layer;
forming a shield region in the drift layer underneath the trench.
24. The method of claim 23 , wherein the spin-on-glass layer comprises boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and/or lead (Pb).
25. The method of claim 23 , further comprising forming a barrier layer on the bottom dielectric layer before forming the gate dielectric layer, where the barrier layer comprises a second material different from the bottom dielectric layer.
26. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure that includes a drift layer having a first conductivity type;
forming a shield region having a second conductivity type in the drift layer underneath the trench;
forming a bottom dielectric layer in the trench;
forming a gate dielectric layer in the trench on the bottom dielectric layer, the gate dielectric layer directly contacting sidewalls of the trench; and
forming a gate electrode in the trench on the bottom dielectric layer,
wherein an upper surface of the bottom dielectric layer is curved.