Gate trench power semiconductor devices having improved breakdown performance and methods of forming such devices
A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.
1 . A semiconductor device, comprising:
a semiconductor layer structure comprising a gate trench formed in an upper surface thereof;
a gate finger in the gate trench;
a supplemental dielectric layer on an upper surface of the gate finger, the supplemental dielectric layer vertically overlapping the gate trench;
a gate connector that includes a first portion that is on an upper surface of a portion of the supplemental dielectric layer that extends beyond a first end of the gate trench and a second portion that is on an upper surface of the gate finger, the gate connector comprising a semiconductor material;
a metal gate bus, wherein the gate connector is positioned in between the semiconductor layer structure and the metal gate bus;
an intermetal dielectric layer that is on an upper surface of the first portion of the gate connector; and
a source contact on an upper surface of the intermetal dielectric layer.
2 . The semiconductor device of claim 1 , further comprising a gate dielectric layer in the gate trench between the semiconductor layer structure and the gate finger.
3 . The semiconductor device of claim 1 , wherein the supplemental dielectric layer directly contacts a portion of the gate dielectric layer that at least partially covers an upper corner of the gate trench.
4 . The semiconductor device of claim 1 , wherein the gate finger extends longitudinally in the gate trench and has a longitudinally-extending upper surface, a longitudinally-extending lower surface, opposed, longitudinally-extending first and second side walls, and opposed first and second end walls, and wherein the supplemental dielectric layer extends over the first end wall of the gate finger.
5 . The semiconductor device of claim 1 , wherein the intermetal dielectric layer vertically overlaps the supplemental dielectric layer.
6 . The semiconductor device of claim 1 , wherein the supplemental dielectric layer vertically overlaps the gate finger along substantially the entire length of the gate finger.
7 . The semiconductor device of claim 6 , wherein the supplemental dielectric layer directly contacts the gate finger along substantially the entire length of the gate finger.
8 . The semiconductor device of claim 1 , wherein the supplemental dielectric layer extends laterally across a full width of the gate finger in at least a portion of an inactive region of the semiconductor device, and the supplemental dielectric layer extends laterally across less than the full width of the gate finger in at least a portion of an active region of the semiconductor device.
9 . The semiconductor device of claim 1 , wherein the gate dielectric layer extends in between a lower surface of the supplemental dielectric layer and the upper surface of the semiconductor layer structure in the region of the semiconductor layer structure that is beyond the first end of the gate trench.
10 . A semiconductor device, comprising:
a semiconductor layer structure comprising a gate trench therein that has a rounded upper corner;
a gate finger in the gate trench;
a gate dielectric layer in the gate trench between the semiconductor layer structure and the gate finger;
a supplemental dielectric layer on an upper surface of the gate dielectric layer and on an upper surface of the gate finger, the supplemental dielectric layer extending above the gate trench and beyond a first end of the gate trench; and
an intermetal dielectric layer that vertically overlaps the supplemental dielectric layer and the gate trench, the intermetal dielectric layer extending beyond the first end of the gate trench above the supplemental dielectric layer.
11 . The semiconductor device of claim 10 , wherein the supplemental dielectric layer directly contacts a portion of the gate dielectric layer that at least partially covers an upper corner of the gate trench.
12 . The semiconductor device of claim 10 , wherein the gate trench extends longitudinally in the semiconductor layer structure and has a longitudinally-extending lower surface, opposed, longitudinally-extending opposed first and second side walls, and opposed first and second end walls, wherein the gate dielectric layer comprises a first portion that extends upwardly along the first end wall of the gate trench, and wherein the supplemental dielectric layer directly contacts the first portion of the gate dielectric layer.
13 . The semiconductor device of claim 10 , further comprising a gate bond pad and a gate bus, the gate finger being electrically connected to the gate bond pad through at least the gate bus, wherein the supplemental dielectric layer comprises a field oxide layer that extends underneath both the gate bond pad and the gate bus.
14 . The semiconductor device of claim 10 , wherein the supplemental dielectric layer comprises at least a portion of a second dielectric layer that directly contacts an upper surface of the semiconductor layer structure adjacent a sidewall of the gate trench, wherein a thickness of the second dielectric layer is at least twice a thickness of the gate dielectric layer.
15 . The semiconductor device of claim 10 , wherein the supplemental dielectric layer vertically overlaps the gate finger along substantially the entire length of the gate finger.
16 . A semiconductor device, comprising:
a semiconductor layer structure having a gate trench therein;
a gate finger in the gate trench;
a gate bus;
a gate connector that electrically connects the gate finger to the gate bus;
a supplemental dielectric layer interposed in between an end portion of the gate finger and the gate connector;
an intermetal dielectric layer that vertically overlaps the supplemental dielectric layer; and
a source contact,
wherein the gate connector extends underneath the source contact,
wherein the supplemental dielectric layer directly contacts a first portion of the gate finger and the intermetal dielectric layer directly contacts a second portion of the gate finger.
17 . The semiconductor device of claim 16 , wherein the gate connector directly contacts both the gate finger and the supplemental dielectric layer.
18 . The semiconductor device of claim 17 , further comprising a gate dielectric layer in the gate trench between the semiconductor layer structure and the gate finger.
19 . The semiconductor device of claim 18 , wherein the supplemental dielectric layer directly contacts a portion of the gate dielectric layer that at least partially covers an upper corner of the gate trench.
20 . The semiconductor device of claim 18 , wherein the supplemental dielectric layer comprises at least a portion of a second dielectric layer that directly contacts an upper surface of the semiconductor layer structure adjacent a sidewall of the gate trench, wherein a thickness of the second dielectric layer is at least four times a thickness of the gate dielectric layer.
21 . The semiconductor device of claim 16 , wherein the gate connector directly contacts the gate finger in between the supplemental dielectric layer and the intermetal dielectric layer.