Power semiconductor devices having multilayer gate dielectric layers that include an etch stop/field control layer and methods of forming such devices
A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.
1. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a source region and a trench formed in the semiconductor layer structure, where at least some corners of the trench are rounded;
a gate dielectric layer on a top surface of the source region and within the trench, the gate dielectric layer comprising lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner;
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure; and
a dielectric isolation pattern on the gate electrode and the gate dielectric layer,
wherein the gate dielectric layer extends laterally beyond sidewalls of the gate electrode and sidewalls of the dielectric isolation pattern.
2. The semiconductor device of claim 1 , wherein the gate dielectric layer comprises a silicon oxide base gate dielectric layer and a capping gate dielectric layer on an upper surface of the silicon oxide base gate dielectric layer.
3. The semiconductor device of claim 2 , wherein a ratio of a thickness of the silicon oxide base gate dielectric layer divided by a dielectric constant of a material of the silicon oxide base gate dielectric layer to a thickness of the capping gate dielectric layer divided by a dielectric constant of a material of the capping gate dielectric layer is at least ten.
4. The semiconductor device of claim 2 , wherein a dielectric constant of the capping gate dielectric layer is at least three times more than a dielectric constant of the silicon oxide base gate dielectric layer.
5. The semiconductor device of claim 2 , wherein the lower corners of the gate dielectric layer comprise rounded corners and the upper corners of the gate dielectric layer comprise rounded corners.
6. The semiconductor device of claim 2 , wherein the corners of the gate dielectric layer that are rounded are lower corners of the gate dielectric layer.
7. The semiconductor device of claim 2 , wherein the corners of the gate dielectric layer that are rounded are upper corners of the gate dielectric layer.
8. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a trench formed therein, where at least some corners of the trench are rounded;
a gate dielectric layer on the semiconductor layer structure-and within the trench, the gate dielectric layer comprising lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner; and
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure
wherein the gate dielectric layer comprises a silicon oxide base gate dielectric layer and a capping gate dielectric layer on an upper surface of the silicon oxide base gate dielectric layer,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the silicon oxide base gate dielectric layer is at least 50% greater than a peak electric field value in the capping gate dielectric layer.
9. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a trench formed therein, where at least some corners of the trench are rounded;
a gate dielectric layer on the semiconductor layer structure-and within the trench, the gate dielectric layer comprising lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner; and
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure
wherein the gate dielectric layer comprises a silicon oxide base gate dielectric layer and first and second capping gate dielectric layers that are on respective lower and upper surfaces of the silicon oxide base gate dielectric layer, where the first and second capping gate dielectric layers each has a dielectric constant that is greater than a dielectric constant of the silicon oxide base gate dielectric layer.
10. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a trench formed therein, where at least some corners of the trench are rounded;
a gate dielectric layer on the semiconductor layer structure-and within the trench, the gate dielectric layer comprising lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner; and
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure
wherein the gate dielectric layer comprises a silicon oxide base gate dielectric layer and a capping gate dielectric layer on an upper surface of the silicon oxide base gate dielectric layer,
wherein the capping gate dielectric layer is thinner than the silicon oxide base gate dielectric layer.
11. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a source region and a trench formed therein;
a gate dielectric layer within the trench, the gate dielectric layer comprising a base gate dielectric layer that is on a top surface of the source region and a first capping gate dielectric layer on the base gate dielectric layer, the first capping gate dielectric layer comprising a different material than the base gate dielectric layer; and
a gate electrode in the trench on the gate dielectric layer opposite the semiconductor layer structure.
12. The semiconductor device of claim 11 , wherein a dielectric constant of the first capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.
13. The semiconductor device of claim 12 , wherein the first capping gate dielectric layer is in between the semiconductor layer structure and the base gate dielectric layer.
14. The semiconductor device of claim 13 , further comprising a second capping gate dielectric layer that is in between the base gate dielectric layer and the gate electrode.
15. The semiconductor device of claim 12 , wherein the first capping gate dielectric layer is in between the base gate dielectric layer and the gate electrode.
16. The semiconductor device of claim 15 , further comprising a second capping gate dielectric layer that is in between the semiconductor layer structure and the base gate dielectric layer.
17. The semiconductor device of claim 11 , wherein the gate dielectric layer comprises lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner.
18. A semiconductor device, comprising:
a silicon carbide semiconductor layer structure that comprises a first conductivity type drift region, and first and second well regions in an upper surface of the first conductivity type drift region, the first and second well regions separated by a JFET region;
a gate dielectric layer on the silicon carbide semiconductor layer structure, the gate dielectric layer comprising a base gate dielectric layer that is on the silicon carbide semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer, the capping gate dielectric layer comprising a different material than the base gate dielectric layer, wherein a dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer, and the capping gate dielectric layer is thinner than a portion of the base gate dielectric layer that is below the capping gate dielectric layer; and
a gate electrode on the gate dielectric layer opposite the silicon carbide semiconductor layer structure.
19. The semiconductor device of claim 18 , wherein the capping gate dielectric layer is not above the JFET region.
20. The semiconductor device of claim 19 , wherein the base gate dielectric layer is in between the capping gate dielectric layer and the silicon carbide semiconductor layer structure.
21. A semiconductor device, comprising:
a silicon carbide semiconductor layer structure that comprises a first conductivity type drift region, and first and second well regions in an upper surface of the first conductivity type drift region, the first and second well regions separated by a JFET region;
a gate dielectric layer on the silicon carbide semiconductor layer structure, the gate dielectric layer comprising a base gate dielectric layer that is on the silicon carbide semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer, the capping gate dielectric layer comprising a different material than the base gate dielectric layer; and
a gate electrode on the gate dielectric layer opposite the silicon carbide semiconductor layer structure,
wherein the gate electrode directly contacts both the capping gate dielectric layer and the base gate dielectric layer, and
wherein the gate dielectric layer extends laterally beyond sidewalls of the gate electrode.
22. The semiconductor device of claim 21 , further comprising a dielectric isolation pattern that covers the gate electrode, wherein the dielectric isolation pattern directly contacts an upper surface of the capping gate dielectric layer.
23. The semiconductor device of claim 22 , wherein a sidewall of the dielectric isolation pattern is aligned with a sidewall of the capping gate dielectric layer.