IP Library › Granted Patent US 12,426,293
Granted Patent B2
US 12,426,293 · App. 17/322,199 · Granted Sep 23, 2025

Group III-nitride transistors with back barrier structures and buried p-type layers and methods thereof

Inventors: Christer Hallin (Hillsborough, NC); Saptharishi Sriram (Cary, NC); Jia Guo (Apex, NC)
Assignee: Wolfspeed, Inc.
H10D30/475H01L21/7605H01L21/765H10D30/015H10D62/824H10D62/8503H10D64/111
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Quick Facts
Patent No.
US 12,426,293
App. No.
17/322,199
Granted
Sep 23, 2025
Kind
B2
Abstract

An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

Claims (170)

1. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain; and

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm;

wherein a part of a source side of the substrate is free of the p-region; and

wherein a part of a drain side of the substrate is free of the p-region.

2. The apparatus of claim 1 , wherein the group III-Nitride back barrier layer comprises the low background impurity levels configured at least in part as a gate lag reduction structure.

3. The apparatus of claim 1 , wherein the p-region is configured at least in part as a drain lag reduction structure; and wherein the group III-Nitride back barrier layer is on a nucleation layer.

4. The apparatus of claim 1 , wherein the group III-Nitride back barrier layer comprises the low background impurity levels configured at least in part as a gate lag reduction structure, the p-region is configured at least in part as a drain lag reduction structure, and the group III-Nitride back barrier layer and the p-region reduce overall lag.

5. The apparatus of claim 1 ,

wherein the group III-Nitride back barrier layer is configured with low background impurity levels of the at least one of the following: silicon, oxygen, and carbon.

6. The apparatus of claim 1 , wherein the group Nitride back barrier layer is configured as a sharp interface to the group III-Nitride channel layer and the sharp interface being configured to function as a barrier for electrons.

7. The apparatus of claim 1 ,

wherein the group III-Nitride back barrier layer is arranged directly on a nucleation layer or directly on the substrate.

8. The apparatus of claim 1 , wherein the group III-Nitride back barrier layer comprises AlGaN with an Al concentration of 1% to 4.5%.

9. The apparatus of claim 1 ,

wherein the group III-Nitride back barrier layer is structured by epitaxial growth with low background impurity levels of at least one of the following: silicon (Si), oxygen (O), and carbon (C).

10. The apparatus of claim 1 , comprising:

a nucleation layer formed on the substrate,

wherein the group III-Nitride back barrier layer is arranged directly on the nucleation layer.

11. The apparatus of claim 1 , wherein the p-region is structured and arranged such that no portion of the p-region is located vertically below the drain.

12. The apparatus of claim 1 , further comprising a field plate, wherein the field plate is electrically coupled to said source.

13. The apparatus of claim 1 wherein the p-region is arranged under and across a length of the gate and extends toward the source and the drain.

14. The apparatus of claim 1 wherein the p-region vertically overlaps the source.

15. The apparatus of claim 1 wherein the p-region extends toward the drain, but does not vertically overlap the drain.

16. The apparatus of claim 1 wherein the p-region comprises no direct electrical connections.

17. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer:

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer:

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain; and

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm;

wherein a portion of the substrate includes the p-region located vertically below the source; and

wherein another portion of the substrate does not include the p-region located vertically below the source.

18. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain; and

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm;

wherein the substrate does not include the p-region located vertically below the source; and

wherein the substrate does not include the p-region located vertically below the drain.

19. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer,

a field plate,

wherein the p-region is implanted;

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain; and

wherein the group III-Nitride back barrier layer is configured with low background impurity levels; and

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm.

20. The apparatus of claim 19 , wherein:

a part of a source side of the substrate is free of the p-region; and

a part of a drain side of the substrate is free of the p-region.

21. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer; and

a field plate, wherein the field plate is electrically coupled to said source,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain;

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm; and

wherein the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer such that the p-region is not located vertically below areas past the source and the drain.

22. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer; and

a field plate, wherein the field plate is electrically coupled to said source,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain;

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm; and

wherein the p-region extends toward the source, but does not vertically overlap the source.

23. An apparatus, comprising:

a substrate;

a group III-Nitride back barrier layer on the substrate;

a group III-Nitride channel layer on the group III-Nitride back barrier layer;

a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

a source electrically coupled to the group III-Nitride barrier layer;

a gate on the group III-Nitride barrier layer;

a drain electrically coupled to the group III-Nitride barrier layer; and

a p-region being arranged at or below the group III-Nitride barrier layer; and

a field plate, wherein the field plate is electrically coupled to said source,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain;

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm; and

wherein the p-region vertically overlaps the drain.

24. A method of making a device comprising:

providing a substrate;

providing a group III-Nitride back barrier layer on the substrate;

providing a group III-Nitride channel layer on the group III-Nitride back barrier layer;

providing a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer;

electrically coupling a source to the group III-Nitride barrier layer;

arranging a gate on the group III-Nitride barrier layer;

electrically coupling a drain to the group III-Nitride barrier layer; and

providing a p-region being arranged at or below the group III-Nitride barrier layer,

wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and area between the gate and the drain;

wherein the group III-Nitride back barrier layer is configured with low background impurity levels;

wherein the low background impurity levels are defined as impurities less than 1E15 per cubic cm;

wherein the group III-Nitride back barrier layer is on a nucleation layer;

wherein the p-region is configured at least in part as a drain lag reduction structure; and

wherein the substrate does not include the p-region located vertically below the source.

25. The method of making the device of claim 24 ,

wherein the group III-Nitride back barrier layer comprises the low background impurity levels configured at least in part as a gate lag reduction structure; and

wherein the group III-Nitride back barrier layer comprises AlGaN with an Al concentration of 1% to 4.5%.

26. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer comprises the low background impurity levels configured at least in part as a gate lag reduction structure, the p-region is configured at least in part as a drain lag reduction structure, and the group III-Nitride back barrier layer and the p-region reduce overall lag.

27. The method of making the device of claim 24 ,

wherein the group III-Nitride back barrier layer comprises the low background impurity levels configured with low background impurity levels of the following: silicon, oxygen, and carbon.

28. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer is arranged directly on a nucleation layer or directly on the substrate.

29. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer is configured as a sharp interface to the group III-Nitride channel layer.

30. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer comprises AlGaN.

31. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer comprises AlGaN with an Al concentration of 1% to 6%.

32. The method of making the device of claim 24 , wherein the group III-Nitride back barrier layer is structured by epitaxial growth with low background impurity levels of at least one of the following: silicon (Si), oxygen (O), and carbon (C).

33. The method of making the device of claim 24 , further comprising a nucleation layer formed on the substrate,

wherein the group III-Nitride back barrier layer is arranged on the nucleation layer.

34. The method of making the device of claim 24 , wherein:

a part of a source side of the substrate is free of the p-region; and

a part of a drain side of the substrate is free of the p-region.

35. The method of making the device of claim 24 , wherein:

a portion of the substrate includes the p-region located vertically below the source; and

another portion of the substrate does not include the p-region located vertically below the source.

36. The method of making the device of claim 24 , wherein:

the substrate does not include the p-region located vertically below the source; and

the substrate does not include the p-region located vertically below the drain.

37. The method of making the device of claim 24 , further comprising forming the p-region such that no portion of the p-region is located vertically below the drain.

38. The method of making the device of claim 24 , further comprising implanting the p-region.

39. The method of making the device of claim 24 , further comprising providing a field plate.

40. The method of making the device of claim 24 , further comprising providing a field plate, wherein the field plate is electrically coupled to said source.

41. The method of making the device of claim 40 , wherein the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer such that the p-region is not located vertically below areas past the source and the drain.

42. The method of making the device of claim 24 wherein the p-region is arranged under and across a length of the gate and extends toward the source and the drain.

43. The method of making the device of claim 24 wherein the p-region extends toward the source, but does not vertically overlap the source.

44. The method of making the device of claim 24 wherein the p-region vertically overlaps the source.

45. The method of making the device of claim 24 wherein the p-region extends toward the drain, but does not vertically overlap the drain.

46. The method of making the device of claim 24 wherein the p-region vertically overlaps the drain.

47. The method of making the device of claim 24 wherein the p-region comprises no direct electrical connections.

48. The method of making the device of claim 24 wherein the p-region is electrically connected to the source.

Assignments (11)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
CHANGE OF NAME Recorded Jul 28, 2025
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 072247/0172 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2025
From: HALLIN, CHRISTER; SRIRAM, SAPTHARISHI; GUO, JIA
To: CREE, INC.
Reel/Frame 071205/0669 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
CHANGE OF NAME Recorded Feb 14, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 059085/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2021
From: HALLIN, CHRISTER; SRIRAM, SAPTHARISHI; GUO, JIA
To: CREE, INC.
Reel/Frame 056272/0971 →
Continuity (1)
Related Publication 20220367697A1 · Nov 17, 2022
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