IP Library Granted Patent US 9,583,607
Granted Patent B2
US 9,583,607 · App. 14/841,967 · Granted Feb 28, 2017

Semiconductor device with multiple-functional barrier layer

Inventors: Koon Hoo Teo (Lexington, MA); Yuhao Zhang (Cambridge, MA)
Assignee: Mitsubishi Electric Research Laboratories, Inc.
H01L29/7784H01L29/2003H01L29/205H01L29/66431H01L29/66462H01L29/778H01L29/7782H01L29/7783H01L29/7786
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Quick Facts
Patent No.
US 9,583,607
App. No.
14/841,967
Granted
Feb 28, 2017
Kind
B2
Abstract

A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and a set of electrodes for providing and controlling carrier charge in the carrier channel. The barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel. The material of the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the semiconductor structure.

Claims (34)

1. A semiconductor device, comprising:

a semiconductor structure forming a carrier channel;

a barrier layer arranged in proximity to the semiconductor structure, wherein the barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel, wherein material of the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the semiconductor structure; and

a set of electrodes for providing and controlling a carrier charge in the carrier channel.

2. The semiconductor device of claim 1 , further comprising:

a substrate, wherein the barrier layer is a back-barrier layer arranged between the substrate and the semiconductor structure.

3. The semiconductor device of claim 1 , wherein the barrier layer is a cap layer arranged on top of the semiconductor structure.

4. The semiconductor device of claim 1 , wherein the material of the barrier layer includes one or combination of diamond, boron nitride and aluminum nitride.

5. The semiconductor device of claim 1 , wherein thickness of the barrier layer is in a range from 10 nm to 10 μm.

6. The semiconductor device of claim 1 , wherein doping concentration of the barrier layer is in a range from 10 15 cm −3 to 10 22 cm −3 .

7. The semiconductor device of claim 1 , wherein the barrier layer extends in parallel with the carrier channel to fully overlap the carrier channel.

8. The semiconductor device of claim 1 , wherein the barrier layer extends in parallel with the carrier channel to only partially overlap the carrier channel.

9. The semiconductor device of claim 1 , wherein thickness, doping concentration and length of the barrier layer are selected to completely deplete charges in the carrier channel at a breakdown voltage of the semiconductor device.

10. The semiconductor device of claim 1 , wherein the semiconductor structure is a semiconductor hetero structure including a III-V channel layer and a III-V barrier layer, such that the carrier channel is a two-dimensional-electron-gas (2DEG) channel, wherein a bandgap of the III-V barrier layer is larger than a bandgap of the III-V channel layer, wherein the barrier layer is fully or partially p-type doped, and the material the back-barrier layer has a larger bandgap and thermal conductivity than the material of the III-V channel layer.

11. The semiconductor device of claim 10 , wherein the material of the III-V channel layer includes one or combination of GaN or GaAs, and wherein the material of the III-V barrier layer includes one or combination of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), aluminum nitride (AlN), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), indium aluminum gallium arsenide (InAlGaAs).

12. A semiconductor device, comprising:

a semiconductor structure forming a carrier channel, wherein the semiconductor structure is a semiconductor heterostructure including a III-V channel layer and a III-V barrier layer, such that the carrier channel is a two-dimensional-electron-gas (2DEG) channel;

a barrier layer arranged proximity to the semiconductor structure, wherein the barrier layer is at least partially p-type doped, wherein the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the III-V channel layer; and

a set of electrodes for providing and controlling carrier charge in the carrier channel.

13. The semiconductor device of claim 12 , wherein the material of the III-V channel layer includes one or combination of GaN or GaAs, and wherein the material of the III-V barrier layer includes one or combination of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), aluminum nitride (AlN), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), indium aluminum gallium arsenide (InAlGaAs).

14. The semiconductor device of claim 12 , wherein the p-type dopants of the barrier layer include one or combination of boron and magnesium.

15. The semiconductor device of claim 12 , wherein the barrier layer extends in parallel with the III-V channel layer to only partially overlap the III-V channel layer.

16. A method for making a semiconductor device, comprising:

providing a substrate;

making a semiconductor structure comprising at least a III-V channel layer forming a carrier channel in the semiconductor structure;

making a barrier layer in proximity to the semiconductor structure, wherein the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the III-V channel layer;

doping the barrier layer with impurities having an opposite conductivity type to the carrier channel; and

forming electrodes in an electrical contact with the carrier channel.

17. The method of claim 15 , further comprising:

forming a buffer layer adjacent to the barrier layer.

18. The method of claim 15 , further comprising:

arranging the barrier layer in parallel with the III-V channel layer to partially overlap the III-V channel layer.

19. The method of claim 15 , wherein the semiconductor structure and the barrier layer are made using one or combination of a Chemical Vapor Deposition (CVD), Metal-Organic Chemical Vapor Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), a Metal-Organic Vapor Phase Epitaxy (MOVPE), a plasma-enhanced chemical vapor deposition (PECVD), and a microwave plasma deposition.

20. The method of claim 15 , wherein the electrodes are formed using one or combination of an electron beam physical vapor deposition (EBPVD), a Joule evaporation, a chemical vapor deposition, and a sputtering process.

Continuity (2)
Provisional Application 62193689 · Jul 17, 2015
Related Publication 20170018638A1 · Jan 19, 2017