Transistor with A-face conductive channel and trench protecting well region
View Patent ↗A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
1. A transistor having an insulated control contact within a trench in a semiconductor crystal structure, the transistor comprising:
a pair of semiconductor mesas defining the trench, said semiconductor mesas each comprising at least one p-n junction;
a buried channel layer extending across portions of top surfaces of said semiconductor mesas and at least partially covering walls of the trench such that said buried channel layer provides a conductive path across an A-face of the semiconductor crystal structure;
a current spreading layer extending between said semiconductor mesas and beneath the bottom of the trench to reduce junction field effect resistance in the transistor; and
a doped well extending from at least one of said semiconductor mesas to a depth within said current spreading layer that is greater than the depth of the trench.
2. A transistor according to claim 1 , wherein the transistor is an A-MOSFET.
3. A transistor according to claim 1 , wherein the transistor is an insulated gate bipolar transistor.
4. A transistor according to claim 1 , wherein the transistor is a metal-oxide-semiconductor controlled thyristor.
5. A transistor according to claim 1 , wherein said doped well is a P+ type well doped to about 1×10 19 cm −3 .
6. A transistor according to claim 5 , wherein one of said p-n junctions within said semiconductor mesas comprises:
a P+ type semiconductor epitaxial layer positioned under said buried channel layer and between the trench and said P+ type well; and
an N+ type source region on said P+ type semiconductor epitaxial layer between the trench and said P+ type well.
7. A transistor according to claim 6 , wherein said P+ type semiconductor epitaxial layer is doped to about 5×10 17 cm −3 and said N+ type source region is doped to about 1×10 20 cm −3 .
8. A transistor according to claim 6 further comprising a buffer layer extending from said doped well to the trench.
9. A transistor according to claim 8 , wherein the at least one p-n junction between said P+ type semiconductor epitaxial layer, said buffer layer, and said P+ type well are sufficiently doped to merge, thereby protecting the trench corner in the off state.
10. An AMOSFET defining walls of a trench for incorporating a gate contact between first and second semiconductor mesas, the trench exposing an A-face of a semiconductor body, the AMOSFET comprising:
a first semiconductor epitaxial layer of a first conductivity type abutting the trench;
a second semiconductor epitaxial layer of a second conductivity type on said first semiconductor epitaxial layer;
a buried channel layer adjacent a first surface of the AMOSFET, said buried channel layer extending across a portion of said second semiconductor epitaxial layer and continuing along a trench wall;
a current spreading layer beneath the bottom of the trench; and
a well region of said first conductivity type extending from said first semiconductor epitaxial layer down into the semiconductor body to a depth greater than the trench.
11. An AMOSFET according to claim 10 , wherein said first conductivity type is P+, and said second conductivity type is N+.
12. An AMOSFET according to claim 10 , wherein the semiconductor body comprises silicon carbide.
13. An AMOSFET according to claim 10 , wherein said buried channel layer extends from an N+ source region of the first semiconductor mesa to an N+ source region within the second semiconductor mesa, thereby covering the walls of the trench.
14. An AMOSFET according to claim 13 , further comprising an N+ type buffer layer between the well region and the trench.
15. A MOSFET for controlling electrical conduction within first and second semiconductor mesas defining walls of a gate trench in a semiconductor body, the MOSFET comprising:
a P+ type semiconductor epitaxial layer abutting the gate trench;
an N+ type source region on said P+ type semiconductor epitaxial layer;
a buried channel layer adjacent a first surface of the MOSFET, said buried channel layer extending across a portion of said N+ type source region and continuing along a trench wall; and
a P+ type well extending from said P+ type semiconductor epitaxial layer down into the semiconductor body to a depth greater than the gate trench;
wherein the MOSFET controls electrical conduction in said buried channel layer along an A-face of the semiconductor body.
16. A MOSFET according to claim 15 , wherein the semiconductor body comprises silicon carbide.
17. A MOSFET according to claim 15 , wherein said buried channel layer extends from an N+ source region within the first semiconductor mesa to an N+ source region within the second semiconductor mesa, thereby covering the trench wall.
18. A MOSFET according to claim 15 , further comprising an N+ type buffer layer between the P+ type well and the gate trench.
19. A MOSFET according to claim 18 , wherein said N+ type buffer layer extends to a depth that is approximately equal to the depth of said buried channel layer.
20. A MOSFET according to claim 15 , further comprising an N+ type drift layer below the gate trench and adjacent said P+ type well, said N+ type drift layer extending toward a surface of the MOSFET opposite said first surface.
21. A MOSFET according to claim 20 , wherein said N+ type drift layer comprises a doping concentration that increases from said opposite MOSFET surface toward said first surface such that the most highly doped region of the N+ type drift layer is adjacent said P+ type well.
22. A MOSFET according to claim 20 , comprising a semiconductor substrate adjacent said N+ type drift layer on the side opposite said P+ type well.
23. A MOSFET according to claim 15 , wherein the gate trench is less than about 2 microns deep.
24. A MOSFET according to claim 15 , wherein the gate trench is less than about 1 micron deep.
25. A MOSFET according to claim 15 , wherein the gate trench is approximately 0.8 microns deep, and said P+ type well is approximately 1.3 microns deep.
26. A MOSFET according to claim 15 , wherein said N+ type source region and said P+ type semiconductor epitaxial layer are at approximately the same fixed potential.