PECVD protective layers for semiconductor devices
View Patent ↗A semiconductor device includes a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a temperature humidity with bias (THB) test exceeding about 1000 hours and/or a highly accelerated stress test (HAST) exceeding about 96 hours. Including a PECVD protective layer capable of protecting the semiconductor device throughout a THB test exceeding about 1000 hours and/or a HAST exceeding about 96 hours results in an extremely robust device, while providing the protective layer via PECVD results in convenience and cost savings.
1. A semiconductor device comprising a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a temperature humidity with bias (THB) test exceeding about 1000 hours, wherein the PECVD protective layer comprises alternating layers of silicon nitride (SiN) and silicon-oxy-nitride (SiON).
2. The semiconductor device of claim 1 wherein the PECVD protective layer is configured to prevent failure of the semiconductor device throughout a THB test exceeding about 1500 hours.
3. The semiconductor device of claim 1 wherein the THB test is performed at about 85° C. and about 85% relative humidity.
4. The semiconductor device of claim 1 wherein the semiconductor device is a transistor.
5. The semiconductor device of claim 4 wherein a gate-to-source voltage of the semiconductor device is biased at about −8V and a drain voltage of the device is biased at about 50V throughout the THB test.
6. The semiconductor device of claim 1 wherein the semiconductor device is a gallium nitride (GaN) device.
7. The semiconductor device of claim 1 wherein a first layer of the PECVD protective layer on the semiconductor device is SiN and a second layer of the PECVD protective layer on the first layer is SiON.
8. A semiconductor device comprising a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a highly accelerated stress test (HAST) exceeding about 96 hours, wherein the PECVD protective layer comprises alternating layers of silicon nitride (SiN) and silicon-oxy-nitride (SiON) and is formed using only silane (SiH 4 ), oxygen (O 2 ), and nitrogen (N 2 ) such that a concentration of SiH 4 to N 2 during the formation of the PECVD protective layer is between 1:100 and 1:1000.
9. The semiconductor device of claim 8 wherein the PECVD protective layer is configured to prevent failure of the semiconductor device throughout a HAST exceeding about 144 hours.
10. The semiconductor device of claim 8 wherein the PECVD protective layer is configured to prevent failure of the semiconductor device throughout a HAST exceeding about 192 hours.
11. The semiconductor device of claim 8 wherein the HAST test is performed at about 130° C., about 85% relative humidity, and about 33 psia (pounds per square inch absolute).
12. The semiconductor device of claim 8 wherein the semiconductor device is a transistor.
13. The semiconductor device of claim 12 wherein a gate-to-source voltage of the semiconductor device is biased at about −8V and a drain voltage of the device is biased at about 50V throughout the HAST test.
14. The semiconductor device of claim 8 wherein the semiconductor device is a gallium nitride (GaN) device.
15. A method of manufacturing a monolithic microwave integrated circuit (MMIC) comprising:
providing the MMIC in a plasma-enhanced chemical vapor deposition (PECVD) chamber;
cleaning at least a surface of the MMIC within the PECVD chamber; and
providing a PECVD protective layer on the MMIC, wherein the PECVD protective layer is configured to prevent failure of the MMIC throughout a temperature humidity with bias (THB) test exceeding about 1000 hours.