IP Library Granted Patent US 12,439,664
Granted Patent B2
US 12,439,664 · App. 17/848,907 · Granted Oct 7, 2025

Methods of forming ohmic contacts on semiconductor devices with trench/mesa structures

Inventors: Madankumar Sampath (Morrisville, NC); Sei-Hyung Ryu (Cary, NC); Rahul R. Potera (Apex, NC)
Assignee: Wolfspeed, Inc.
H10D62/85H01L21/28575H10D62/8325H10D64/62
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Quick Facts
Patent No.
US 12,439,664
App. No.
17/848,907
Granted
Oct 7, 2025
Kind
B2
Abstract

A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Claims (58)

1. A method of forming ohmic contacts on a semiconductor structure having a trench and a mesa adjacent the trench, the method comprising:

forming a dielectric layer in the trench;

depositing a first metal on a top surface of the mesa;

removing the dielectric layer from the trench;

after removing the dielectric layer from the trench, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the top surface of the mesa;

depositing a second metal on a bottom surface of the trench; and

annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature to form a second ohmic contact to the bottom surface of the trench.

2. The method of claim 1 , wherein the semiconductor structure has a first conductivity type at the top surface of the mesa and a second conductivity type at the bottom surface of the trench.

3. The method of claim 2 , wherein the semiconductor structure comprises silicon carbide, wherein the first conductivity type is n-type and the second conductivity type is p-type.

4. The method of claim 1 , wherein the first metal and the second metal comprise a same metal.

5. The method of claim 4 , wherein the first metal and the second metal comprise nickel.

6. The method of claim 1 , wherein the first metal and the second metal comprise different metals.

7. The method of claim 6 , wherein the first metal comprises titanium or nickel, and the second metal comprises aluminum or platinum.

8. The method of claim 1 , wherein the first contact anneal temperature is greater than 750 C.

9. The method of claim 1 , wherein the first contact anneal temperature is between 800 C and 1200 C.

10. The method of claim 9 , wherein the second contact anneal temperature is between 650 C and 1000 C.

11. The method of claim 9 , wherein annealing the structure to form the second ohmic contact comprises annealing the structure at a sufficient temperature to form a metal silicide layer on the bottom surface of the trench.

12. The method of claim 1 , further comprising:

before removing the dielectric layer from the trench, annealing the structure at a third contact anneal temperature that is lower than the first contact anneal temperature.

13. The method of claim 12 , wherein the third contact anneal temperature is sufficient to form a metal silicide layer at the top surface of the mesa.

14. The method of claim 12 , wherein the third contact anneal temperature is between 500 C and 800 C.

15. The method of claim 12 , wherein the third contact anneal temperature is greater than 700 C.

16. The method of claim 1 , wherein annealing the structure to form the first ohmic contact comprises annealing the structure in a furnace, and wherein annealing the structure to form the second ohmic contact comprises performing a rapid thermal anneal of the structure.

17. The method of claim 1 , wherein the structure comprises a junction field effect transistor or an insulated gate bipolar transistor structure.

18. The method of claim 1 , wherein forming the dielectric layer in the trench comprises:

forming the dielectric layer on the semiconductor structure, wherein the dielectric layer covers the mesa and fills the trench; and

selectively removing a portion of the dielectric layer above the mesa to expose a top surface of the mesa.

19. The method of claim 18 , wherein selectively removing the portion of the dielectric layer comprises planarizing the structure.

20. The method of claim 1 , wherein the first ohmic contact and the second ohmic contact each have a contact resistance less than 1E-3 Ω-cm 2 .

21. The method of claim 1 , wherein the first ohmic contact and the second ohmic contact each have a contact resistance less than 1E-4 Ω-cm 2 .

22. The method of claim 1 , wherein the first ohmic contact and the second ohmic contact are separated from one another.

23. A method of forming ohmic contacts on a semiconductor structure having a trench and a mesa, the method comprising:

forming a mask on a top surface of the mesa;

depositing a first metal on a bottom surface of the trench;

removing the mask from the mesa;

annealing the structure at a first contact anneal temperature to form an ohmic contact on the bottom surface of the trench;

depositing a second metal on the top surface of the mesa; and

annealing the structure at a second contact anneal temperature that is less than the first contact anneal temperature to form a second ohmic contact to the top surface of the mesa.

24. A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region, the method comprising:

depositing a first metal on the n-type region;

annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region;

depositing a second metal on the first ohmic contact and on the p-type region; and

annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature to form a second ohmic contact on the p-type region;

wherein the method further comprises:

forming a mask on the p-type region prior to depositing the first metal, wherein the first metal is deposited onto the mask;

annealing the structure at a third anneal temperature that is less than the first contact anneal temperature; and

removing the mask after annealing the structure at the third anneal temperature.

25. A method of forming ohmic contacts on a semiconductor structure having a trench and a mesa, the method comprising:

depositing a first metal on the bottom surface of the trench;

annealing the structure at a first contact anneal temperature to form a first ohmic contact on the bottom surface of the trench;

depositing a second metal on a top surface of the mesa; and

annealing the structure at a second contact anneal temperature that is less than the first contact anneal temperature to form a second ohmic contact to the top surface of the mesa;

wherein the method further comprises:

forming a mask on the top surface of the mesa prior to depositing the first metal on the bottom surface of the trench; and

removing the mask from the top surface of the mesa after depositing the first metal on the bottom surface of the trench.

26. The method of claim 25 , wherein the top surface of the mesa comprises a p-type material and the bottom surface of the trench comprises an n-type material.

27. The method of claim 25 , wherein the first contact anneal temperature is between 800 C and 1200 C.

28. The method of claim 25 , wherein the second contact anneal temperature is between 650 C and 1000 C.

Assignments (7)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2022
From: SAMPATH, MADANKUMAR; RYU, SEI-HYUNG; POTERA, RAHUL R.
To: WOLFSPEED, INC.
Reel/Frame 060770/0220 →